Showing papers on "Gate driver published in 2018"

A 6.7-GHz Active Gate Driver for GaN FETs to Combat Overshoot, Ringing, and EMI

Abstract: Active gate driving has been demonstrated to beneficially shape switching waveforms in Si- and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 Ω. A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating high-frequency spectral content.

IGBT Junction Temperature Estimation via Gate Voltage Plateau Sensing

Abstract: A method for in situ high-bandwidth junction temperature estimation of insulated-gate bipolar transistors is introduced in this paper. The method is based on the acquisition of the gate voltage plateau during turn- on . It can be related to the junction temperature at any known device current, that can be effectively approximated using existing phase current measurements. This allows fast overtemperature protection of the power device or even active thermal cycle reduction via thermal control. This paper discusses, first, the physical mechanisms leading to the temperature sensitivity of the gate voltage plateau. Second, a rigorous sensitivity analysis of the gate voltage plateau is conducted. It allows to determine the maximal estimation error and provides information about the suitability of this method for various devices and applications. Finally, a sensing circuitry is presented, which allows accurate gate voltage plateau sensing every switching period as well as an easy integration into the gate driver. The performance of the proposed method is experimentally demonstrated with the sensing circuitry on a double pulse test bench over a wide operation range.

Automatic, highly reliable, fully redundant electronic circuit breaker that reduces or prevents short-circuit overcurrent

Abstract: A programmable power (PPSE) switching element including a front power transistor, a main switching transistor, and at least one reverse current blocking transistor in series, a gate of each of which is connected to a gate driver; an inductor and a shunt resistor connected in series with the transistors; a charge storage capacitor connected between ground and a junction located between the inductor and the shunt resistor; a high-speed NPN transistor, a collector of which is connected to the front power transistor and an emitter of which is connected to an output of the main switching transistor via the shunt resistor; a current measurement element in parallel to the shunt resistor; a voltage amplifier; and a high-speed MCU.

High-speed, high-reliability GaN power device with integrated gate driver

Abstract: An enhancement-mode GaN power switch with monolithically integrated gate driver is demonstrated on a 650-V GaN-on-Si power device platform. The integrated GaN-based gate driver features advanced designs such as bootstrapped gate-charging current source that enables high current driving capability during the entire turn-on process and rail-to-rail output. The GaN power transistor with integrated gate driver was characterized up to 300 V/15 A switching operations using a double pulse tester, and exhibits suppressed gate ringing and fast switching speed. The peak drain voltage slew rate d V/dt is above 125 V/ns during turn-on, and 336 V/ns during turn-off.

Comparative Study on Multiple Degrees of Freedom of Gate Drivers for Transient Behavior Regulation of SiC MOSFET

Abstract: Because of fast switching speeds and inevitable stray parameters, the efficiency, security, and stability properties of SiC mosfet s in practice are challenged by voltage and current ringing and overshoot. In this paper, the turn-on and off behavior of an SiC mosfet regulated by a gate driver are modeled in detail, and insight mechanisms for suppressing the ringing and overshoot by using gate driver are highlighted. Based on a clamped inductive double-pulse test, many control degrees of freedom, including gate resistance, gate–source capacitance, and gate voltage, are considered and verified by comprehensive experimental results. Although these parameters can regulate the ringing and overshoot, the switching speed of the SiC mosfet decreases and its power loss increases. To balance the tradeoff, a preferred gate driver for an SiC mosfet is recommended.

A Tri-Slope Gate Driving GaN DC–DC Converter With Spurious Noise Compression and Ringing Suppression for Automotive Applications

Abstract: Targeting on electromagnetic interference (EMI) regulation and ringing suppression issues in automotive applications, this paper presents a gallium nitride (GaN)-based dc–dc converter operating at 10 MHz. A spurious noise compression technique compresses and re-distributes spurious switching noise within a defined frequency sideband, achieving EMI noise reduction at main switching frequency and its harmonics. Meanwhile, a tri-slope gate driver is designed to control voltage and current slew rates of GaN switches for effective ringing suppression, which is adaptive to load and input voltage changes. Tailored for high switching frequency and high-efficiency operation, the dynamic level shifters achieve about 0.8-ns propagation delay and near-zero quiescent current. Fabricated in a 0.35- $\mu$ m Bipolar-CMOS-DMOS process, the converter accomplishes an EMI noise reduction of 40.5 dB $\mu$ V and suppresses $V_{\text {SW}}$ ringing by 79.3%. The converter retains above 60% efficiency over 96.6% of its 6-W power range, with a peak efficiency of 85.5% at 1.5-W load.

A Gate Driver of SiC MOSFET for Suppressing the Negative Voltage Spikes in a Bridge Circuit

Abstract: SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet , which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfet s under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated.

An Ultralow Loss Inductorless $dv/dt$ Filter Concept for Medium-Power Voltage Source Motor Drive Converters With SiC Devices

Abstract: In this paper, a novel $dv/dt$ filter is presented targeted for 100-kW to 1-MW voltage source converters using silicon carbide (SiC) power devices. This concept uses the stray inductance between the power device and the converter output as a filter component in combination with an additional small RC -link. Hence, a lossy, bulky, and costly filter inductor is avoided and the resulting output $dv/dt$ is limited to 5–10 kV/ $\mu$ s independent of the output current and switching speed of the SiC devices. As a consequence, loads with $dv/dt$ constraints, e.g., motor drives can be fed from SiC devices enabling full utilization of their high switching speed. Moreover, a filter-model is proposed for the selection of filter component values for a certain $dv/dt$ requirement. Finally, results are shown using a 300-A 1700-V SiC metal–oxide–semiconductor field-effect transistor ( mosfet ). These results show that the converter output $dv/dt$ can be limited to 7.5 kV/ $\mu$ s even though values up to 47 kV/ $\mu$ s were measured across the SiC mosfet module. Hence, the total switching losses, including the filter losses, are verified to be three times lower compared to when the mosfet $dv/dt$ was slowed down by adjusting the gate driver.

Active Gate Control in Half-Bridge Inverters Using Programmable Gate Driver ICs to Improve Both Surge Voltage and Converter Efficiency

Abstract: The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit.

Advanced Active Gate Drive for Switching Performance Improvement and Overvoltage Protection of High-Power IGBTs

Abstract: This paper presents a new active gate drive (AGD) for switching performance improvement and overvoltage protection of high-power insulated gate bipolar transistors (IGBTs). In addition to the conventional gate drive (CGD) based on fixed voltage sources and fixed gate drive resistors, the proposed AGD has a complementary current source to provide extra gate drive current into the gate. Specific transient switching stages of the IGBT can be therefore accelerated, leading to higher switching speed and lower switching loss of the IGBT. Additionally, the turn-off voltage overshoot of the IGBT can be controlled at a preset reference value with a fast closed-loop overvoltage protection circuit. Moreover, the switching speed of the IGBT, including the turn-on/off delay times and the turn-on/off voltage slopes, can be effectively regulated with an adaptive switching speed control method. Accordingly, the gate drive is capable of operating the IGBT at specified delay times and fixed voltage slopes when varying the switching conditions (e.g., temperature, load current). The operation principle of the proposed AGD and control concept are presented. By comparing with the CGD, the proposed method is experimentally verified on a 3.3 kV/1.5 kA IGBT module in both double-pulse and multipulse tests.

Design and Testing of 1 kV H-bridge Power Electronics Building Block Based on 1.7 kV SiC MOSFET Module

Abstract: This paper presents a part of the design for a power electronics building block (PEBB) based on 10 kV SiC MOSFET power module. A H-bridge PEBB system architecture is introduced at the beginning, followed by the design details of a smart gate driver. Strong noise-immunity, high driving current and effective protection circuitry have been accomplished. The design of power supply that feeds the gate drivers while providing 10 kV galvanic isolation is also shown. A resonant current bus (RCB)-based topology is proposed to supply the gate drivers, achieving both high density and low input-output capacitance of the isolation. Finally, a 10 kV laminated DC bus-bar with new layer-stacking structure is presented. Experimental results are embedded in each section to validate the PEBB performance.

Novel Control Scheme for an Interleaved Flyback Converter Based Solar PV Microinverter to Achieve High Efficiency

Abstract: The paper proposes an optimal control strategy for the interleaved flyback based microinverter to improve its efficiency over the entire operating range. This control scheme is based on the choice of an appropriate operating mode [1-converter discontinuous conduction mode (DCM), 1-converter boundary conduction mode (BCM), 2-converter DCM, and 2-converter BCM] at various instantaneous power magnitudes. The proposed control method reduces the fixed losses associated with the gate driver and the transformer at the low power level. It also reduces the switching losses that may result due to the extremely high-frequency operation of the BCM at the low power level. Additionally, it also reduces the conduction losses through low current peak due to BCM and equal current sharing between the two converters at the high power level. Switching losses, due to the low-frequency operation of the BCM at a high power level, are also reduced. Operating mode selection of the interleaved inverter at a particular power level is based on the information of optimal efficiency. Detailed calculations of peak current references have been carried out for the various operating modes of the interleaved flyback based microinverter. Simulation and experimental results have validated that the proposed control method results in better efficiency compared with the conventional (DCM, hybrid DCM/BCM, hybrid 1-converter/2-converter) control methods with the output current total harmonic distortion remaining within the specified limits.

An Integrated Gate Driver with Active Delay Control Method for Series Connected SiC MOSFETs

Abstract: Series connected SiC MOSFETs technology can apply low rated voltage power device to medium or high voltage applications However, voltage unbalance problem limits its performance In this paper, an integrated gate driver with active delay control method for series connected SiC MOSFETs is presented to achieve voltage balance The main idea is to delay the drive signal for a time period to compensate its deviation between different SiC MOSFET The delay action is implemented by a delay line IC to adapt the fast switching process of SiC MOSFET The proposed gate driver provides a closed loop control for series connected SiC MOSFETs It can effectively balance the voltage without slowing down the switching speed or inducing extra losses, and the effectiveness of the proposed gate driver has been verified by experimental results

Experimental investigation on the transient switching behavior of SiC MOSFETs using a stage-wise gate driver

Abstract: A multiple stage gate driver for SiC MOSFETs based on a switched resistor topology is introduced and a hardware realization is presented. The measurement setup is shown in detail to highlight the quality of the shown measurement results. The evaluation of the stage-wise driver is conducted by comparing the switch and diode peak voltages as well as peak currents with regard to the switching losses to a reference driver. The switching transients are generated using a double pulse test bench. A detailed investigation on two- and three-stage operation for both, the turnon and turn-off events are presented. A variation of gate resistors and different timings is conducted for each stage and evaluated using the resulting measurements. It is shown that the drain-source peak voltage is reduced by 45% while maintaining equal turn-off losses. Analogously, a reduction of 51% of the diode peak voltage and a reduction of 50% of the peak reverse recovery current at the same time is feasible for equal turn-on losses.

A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors

Abstract: Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage V t of ∼1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop V F across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to V F , 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.

Real-Time Junction Temperature Sensing for Silicon Carbide MOSFET With Different Gate Drive Topologies and Different Operating Conditions

Abstract: The switching transient properties from the switching power semiconductor gate side are sensitive to the device's junction temperature ( $T_{j}$ ) Real-time $T_{j}$ sensing methods based on gate drive switching transient properties have been investigated on silicon MOSFET and silicon IGBT, with a conventional push–pull-type gate drive, under fixed dc-bus voltage In this paper, this method is applied to silicon-carbide (SiC) MOSFET The $T_{j}$ sensing methods are evaluated with different types of gate drive topologies By implementing the SiC MOSFETs into an H-bridge inverter, the effect of dc-bus voltage for the $T_{j}$ sensing method is investigated Different “gate drive−semiconductor” dynamic models are built, including gate drive output power stage, gate drive parasitics, SiC MOSFET intrinsic parameters, and PCB parasitics Experimental results are compared with circuit LTSpice model simulation The device vertical temperature contours are evaluated Suitable circuitry for $T_{j}$ sensitivity extraction is provided

Active Gate Driving Technique for a 1200 V SiC MOSFET to Minimize Detrimental Effects of Parasitic Inductance in the Converter Layout

Abstract: 1200 V SiC mosfet is a suitable replacement for Si insulated gate bipolar transistors due to its improved switching behavior. However, high $di/dt$ and $dv/dt$ of SiC mosfet cause very high voltage overshoot and oscillations due to the presence of parasitic inductance in the converter layout and parasitic capacitance of the load. These undesired switching responses increase switching loss and give rise to electromagnetic interference related issues. Therefore, it is important to minimize these adverse effects in order to extract maximum benefits from SiC mosfet . This paper proposes an active gate driving technique for SiC mosfet to improve its overall switching performance in the presence of a moderately higher amount of parasitic inductance in the converter layout. It is achieved by controlling the device $di/dt$ and $dv/dt$ independently in four stages, with appropriate values of gate resistances for both turn- on and turn- off switching transient. The developed active gate driver is tested in a double-pulse test bed and a two-level voltage source inverter driving an induction motor load.

Monolithically integrated power circuits in high-voltage GaN-on-Si heterojunction technology

Abstract: This study presents monolithically integrated power circuits, fabricated in a high-voltage GaN-on-Si heterojunction technology. Different advanced concepts are presented and compared with solutions found in the literature. High switching transition slew rates are demonstrated by means of a monolithic power circuit with integrated gate driver. A highly linear temperature sensor is integrated in a GaN-high-electron-mobility transistor (HEMT) power device for the 600 V class and on-state resistance of 53 mΩ. An area-efficient HEMT structure with integrated freewheeling diodes is presented. This structure is applied in a monolithic multilevel converter chip, as well as in a 600 V class half-bridge chip. The multilevel chip is integrated by an advanced printed circuit board embedding technology and tested in inverter operation with a mains voltage output of 120 V RMS . The performance of the half-bridge is demonstrated in a synchronous buck converter operation from 400 to 200 V and with a switching frequency of 3 MHz.

Miller plateau as an indicator of SiC MOSFET gate oxide degradation

Abstract: This paper presents a new indicator of SiC MOSFET gate oxide degradation based on Miller plateau. The physical mechanism of Miller plateau shift with gate oxide electric field is first analyzed. The relationship between Miller plateau and ambient temperature is then explored by theoretical analysis. The electro-thermal simulation is conducted in LTSpice to verify the Miller plateau shift with ambient temperature. Besides, 20 groups of High Electric Field (HEF) acceleration tests are conducted with V gs stress amplitude of 25 V, 30V, 35V, 40V and stress duration of 10, 40, 70, 85, 100 hours. 5 SCT2120AF SiC MOSEFTs from Rohm are stressed in each group. After ageing tests, the stressed devices are used to verify dynamic characteristic change in the designed double pulse test platform. After 100-hour HEF tests with 40V V gs stress, Miller plateau shift can reach up to 1.5V. Finally, comparison is made among Miller plateau, threshold voltage and gate resistor turn-on energy. Analysis shows that Miller plateau can be used as an indicator of SiC MOSFET gate oxide degradation with detectable amplitude shift as well as inherent gate driver integration and online monitoring characteristics.

Phase Current Sensor and Short-Circuit Detection based on Rogowski Coils Integrated on Gate Driver for 1.2 kV SiC MOSFET Half-Bridge Module

Abstract: Silicon-carbide (SiC) MOSFETs are enabling electrical vehicle motor drives to meet the demands of higher power density, efficiency, and lower system cost. Hence, this paper seeks to explore the benefits that a gate-driver-level intelligence can contribute to SiC-based power inverters. The intelligence is brought by PCB-embedded Rogowski switch-current sensors (RSCS) integrated on the gate driver of a 1.2 kV, 300 A SiC MOSFET half-bridge module. They collect two MOSFET switch currents in a manner of high magnitude, high bandwidth, and solid signal isolation. The switch-current signals are used for short-circuit detection under various fault impedances, as well as for phase-current reconstruction by subtracting one switch current from another. The fundamentals and noise-immunity design of the gate driver containing the RSCS are presented in the paper and can be applied to any half-bridge power module. A three-phase inverter prototype has been built and operated in continuous PWM mode. On this setup, the performance and limitations of the short-circuit detection and phase-current reconstruction are experimentally validated by comparing with commercial current probes and Hall sensors.

Comprehensive Study on Gate Driver for SiC-MOSFETs with Gate Boost

Abstract: This paper presents a high-speed, low loss, and low noise gate driver for silicon-carbide (SiC) MOSFETs. We propose a gate boost circuit to reduce the switching loss and delay time without increasing the switching noise. The proposed gate driver enables converter-level efficiency improvements or power density enhancements. SiC MOSFETs have attracted significant interest as the next generation power devices. In general, the switching performance of power devices exhibits a trade-off between switching loss and noise. SiC-MOSFETs are expected to switch faster than Silicon IGBTs; however, faster switching might cause switching noise problems such as unwanted electromagnetic interferences (EMI). In this paper, we propose a gate driver topology that improves the switching performance of SiC-MOSFETs, and confirm the reduction in switching loss and delay time through experimental results.

Gate Driver Supply Architectures for Common Mode Conducted EMI Reduction in Series Connection of Multiple Power Devices

Abstract: This paper presents a study on the gate driver circuitries that need to be implemented to drive several power devices when associated in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated. In a gate driver circuitry for a regular low side–high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primary-secondary parasitic capacitance of gate driver supplies, and control signal isolation units are the reasons for the generation of conducted electromagnetic interference (EMI) perturbations. In complex power converters, multicell, multilevel, or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, this paper analyzes the best configuration to minimize parasitic currents, especially reducing the conducted common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis for two power devices in series connection, and then the extrapolations for more power devices in series connection, up to six are discussed and analyzed with the help of simulations results.

Integrated Gate Drivers Based on High-Voltage Energy Storing for GaN Transistors

Abstract: This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high-voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gate-driving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.

A High-Speed Gate Driver with PCB-Embedded Rogowski Switch-Current Sensor for a 10 kV, 240 A, SiC MOSFET Module

Abstract: High-voltage SiC MOSFET modules are revolutionizing modern high power electronics owing to their high blocking voltage, low conduction resistance, and fast switching frequency. A 10 kV, 240 A SiC MOSFET module has recently become a candidate to build medium-voltage converters. The MOSFET module comprises three independent submodules that can be configured as three phase-legs, or one half-bridge by paralleling. To maximize its performance, this paper presents a smart gate driver design for this particular semiconductor device. The design concentrates on a high-current booster stage and a high-bandwidth PCB-embedded Rogowski switch-current sensors for the paralleled submodules. The PCB layout has satisfied high-voltage clearance and creepage standards. Finally, the booster current sharing and RSCS performance have been experimentally validated.

An FPGA-Based Voltage Balancing Control for Multi-HV-IGBTs in Series Connection

Abstract: The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. The effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

Design of a Medium Voltage Mobile Utilities Support Equipment based Solid State Transformer (MUSE-SST) with 10 kV SiC MOSFETs for Grid Interconnection

Abstract: A conventional transformer can withstand multiple electrical, mechanical and thermal faults which enables it to have a long lifetime. However, its inability to control the power flow through it has led researchers to look for alternate options such as the solid-state transformers. With the Silicon Carbide (SiC) semiconductor devices, it is now possible to go to high switching frequencies in medium voltage applications, which helps in reducing the overall size and weight of the transformer. The advent of medium voltage (MV) SiC devices has enabled the use of simple two-level and three-level topologies for medium voltage power transfer. This paper discusses a basic power topology for a medium voltage mobile utilities support equipment based solid state transformer (MUSE-SST) with the new 10 kV SiC MOS-FETs. A design of the MUSE-SST is presented followed by some of the practical considerations that needs to be taken, including gate driver design and heat sink configurations. Simulation results for a 100 kW, MV MUSE SST system is presented. Experimental results are provided validating the operation of these 10 kV devices in double pulse tests, buck and boost operation. This research helps in providing an overview regarding the usage of the 10 kV SiC devices in grid-interconnection and also discusses various challenges that comes along with it.

Active Thermal Control of GaN-Based DC/DC Converter

Abstract: The new packaging technologies used for gallium nitride (GaN) devices avoid wire bonds and leads in order to completely utilize their switching performance. This also means that thermomechanical fatigue that used to exist within the device may no longer be a reliability problem. And one of the main bottlenecks for reliability will be the solder joints between the device and the printed circuit board (PCB). To limit the thermal cycling induced failures in these points, an active thermal control scheme using a two step gate driver designed for GaN is presented in this paper. In contrast to the active thermal control techniques employing variable switching frequency control, this method does not alter the converter operation frequency; instead, it merely controls the GaN device slew rates. A simple temperature control algorithm that actively varies the device losses with the objective to minimize thermal cycling is proposed. The solder fatigue due to thermal cycling has been discussed. The effectiveness of this active thermal control scheme has been analyzed also in comparison with losses and validated with analysis, simulation, and experimental results.

A High-Temperature Gate Driver for Silicon Carbide mosfet

Abstract: SiC MOSFET can operate at a junction temperature of 200–250 $^{\circ }$ C due to its improved material properties and thermal stability. However, successful realization of SiC MOSFET based high-temperature (HT) converter requires HT gate drivers. This paper presents a low-cost HT gate driver developed with discrete transistors and signal diodes rated at 180–200 $^{\circ }$ C. The gate driver has a robust overcurrent and undervoltage lock out protection circuit. The propagation delay of the protection circuit and gate driving circuit is greatly reduced compared to commercial HT gate drivers. A comparative analysis of the developed HT gate driver using discrete components and the commercially available silicon-on-insulator technology based HT gate driver is presented. The performance of the HT gate driver is evaluated for both hard switched fault and fault under load condition at an ambient temperature of 180 $^{\circ }$ C.