Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Design of a 250 kW, 1200 V SiC MOSFET-based three-phase inverter by considering a subsystem level design optimization approach

Abstract: Silicon carbide (SiC) power semiconductor technology has successfully penetrated several silicon (Si) application markets and is gaining momentum due to higher voltage withstand capability, higher switching capabilities (i.e., 100s of kHz), and ability to withstand higher operating temperatures (i.e., more than 200°C). When properly applied, SiC MOSFETs can switch in nanoseconds making this a promising candidate for high-power, high-temperature, highspeed, and high-efficiency power converter applications. In fact, many consider the SiC MOSFET as the most “ideal” power semiconductor switch developed to date. To maximize the benefit of this fast switching power device, it is necessary to exercise extraordinary care when designing the power converter's subsystems. In this paper, an approach based on a subsystem optimization approach is presented wherein the power module, the DC and AC bus structures, the DC link capacitor bank, and the gate driver controls are discussed for a 16 kg, 250 kW all-SiC three-phase inverter.

Gate Driver Supply Architectures for Common Mode Conducted EMI Reduction in Series Connection of Multiple Power Devices

Abstract: This paper presents a study on the gate driver circuitries that need to be implemented to drive several power devices when associated in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated. In a gate driver circuitry for a regular low side–high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primary-secondary parasitic capacitance of gate driver supplies, and control signal isolation units are the reasons for the generation of conducted electromagnetic interference (EMI) perturbations. In complex power converters, multicell, multilevel, or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, this paper analyzes the best configuration to minimize parasitic currents, especially reducing the conducted common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis for two power devices in series connection, and then the extrapolations for more power devices in series connection, up to six are discussed and analyzed with the help of simulations results.

Voltage/current control apparatus and method

Abstract: A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”.

2-D–3-D Switchable Gate Driver Circuit for TFT-LCD Applications

Abstract: This paper presents a novel 2-D–3-D switchable gate driver circuit for active-matrix liquid crystal displays (AMLCDs) applications using the hydrogenated amorphous silicon (a-Si:H) technology. While consisting of 12 thin-film transistors (TFTs), the proposed gate driver circuit includes a pull-up circuit, two alternative circuits, and a key pull-down circuit. To provide a stable output waveform for switching between the 2-D and 3-D modes in AMLCD panel, the proposed circuit can improve the threshold voltage shift of a-Si:H TFT using reversed bias stress. Based on a real circuit integrated on glass with a standard five-mask process applied to a large-sized FHD TFT-LCD panel, the layout area of each gate driver circuit is 359.25 $\mu{\rm m}\times\,$ 2296.25 $\mu{\rm m}$ . In addition, the power consumption of a 12-stage gate driver circuit is 3.25 and 7.21 mW, while operating at 2-D and 3-D modes, respectively. Measurement results indicate that the output waveform, including output voltage, rising time, and falling time can be stabilized and made almost equal to the initial state after the reliability test at 100 $^{\circ}{\rm C}$ over 240 h.