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Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.


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Patent
27 Dec 2005
TL;DR: In this article, a gate driver for a display device includes a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and a dummy clock provided to the plurality of shifts during a vertical blank time to reduce a stress voltage in the shift registers, wherein an output of each shift register is reset to a low state power supply voltage by an output signal of the next shift register.
Abstract: A gate driver for a display device includes a plurality of shift registers to sequentially generate output signals during a frame period in response to multi-phase clocks; and a dummy clock provided to the plurality of shift registers during a vertical blank time to reduce a stress voltage in the shift registers, wherein an output of each of the shift registers is reset to a low state power supply voltage by an output signal of the next shift register.

29 citations

Patent
Song Ryol You1
28 Jun 2007
TL;DR: In this paper, an apparatus and method for driving an LCD device to obtain rapid response speed and to enhance picture quality is described, in which the apparatus includes a liquid crystal panel that includes liquid crystal cells formed in areas defined by gate and data lines.
Abstract: An apparatus and method for driving an LCD device is disclosed to obtain rapid response speed and to enhance picture quality, in which the apparatus includes a liquid crystal panel that includes liquid crystal cells formed in areas defined by gate and data lines; a gate driver that supplies a scan pulse to the gate lines; a timing controller that modulates source data supplied from the external to modulated data for a rapid response speed of liquid crystal cell, and generates discrimination signals by comparing source data of a current frame with uppermost and lowermost gray scales of source data based on whether source data of a current frame is the same as source data of a previous frame or not; and a data driver that converts the modulated data into a video signal by using a plurality of gamma voltages including a first modulation voltage that is higher than an maximum gamma voltage or a second modulation voltage that is lower than a minimum gamma voltage, and supplies the video signal to the data lines.

29 citations

Journal ArticleDOI
TL;DR: A fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max.
Abstract: This paper presents a fully integrated gate driver in a 180-nm bipolar CMOS DMOS (BCD) technology with 1.5-A max. gate current, suitable for normally OFF gallium nitride (GaN) power switches, including gate-injection transistors (GIT). Full-bridge driver architecture provides a bipolar and three-level gate drive voltage for a robust and efficient GaN switching. The concept of high-voltage energy storing (HVES), which comprises an on-chip resonant LC tank, enables a very area-efficient buffer capacitor integration and superior gate-driving speed. It reduces the component count and the influence of parasitic gate-loop inductance. Theory and calculations confirm the benefits of HVES compared to other capacitor implementation methods. The proposed gate driver delivers a gate charge of up to 11.6 nC, sufficient to drive most types of currently available GaN power transistors. Consequently, HVES enables to utilize the fast switching capabilities of GaN for advanced and compact power electronics.

29 citations

Patent
27 Feb 2004
TL;DR: The floating gate transistor as mentioned in this paper provides a high gain memory cell and low voltage operation for DRAM and flash EEPROM memory with a low barrier energy at an interface with an adjacent gate insulator.
Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

29 citations

Journal ArticleDOI
TL;DR: In this article, an active method for zero current switching for resonant switched capacitor converters (SCCs) with wide dynamic range is presented, where the sensing signals of the resonant currents are obtained from the flying capacitors rather than form element in which the current includes a dc component.
Abstract: This paper introduces an active method for zero current switching for resonant switched capacitor converters (SCC) with wide dynamic range. The method is demonstrated on a binary SCC that features wide range of conversion ratios. Due to the resultant high efficiency of the converter operating under soft-switching conditions, it is applicable for higher power levels up to the medium power range (100 W). The resonant operation is achieved with a single air core inductor and precise commutation at zero current. The sensing signals of the resonant currents are obtained from the flying capacitors rather than form element in which the current includes a dc component. The zero detection method developed is capable of compensating for both the processing delays (from detection to switching action) and for the large variations of the resonant characteristics (due to transition between subcircuits), and for any other component variations. A 100 W prototype with maximum input voltage of 100 V and up to 19 conversion ratios has been built and tested experimentally. The current sensing has been implemented with a simple, cost-efficient, passive sensor. For proper construction of a higher power experimental prototype with desired target efficiency, a set of design considerations for the selection of the power stage components, based on an expanded equivalent resistance concept for multiple subcircuits converter, has been delineated. In addition, a simple and efficient isolated gate driver circuitry is presented.

29 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202351
202297
2021235
2020372
2019425
2018449