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Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.


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Proceedings ArticleDOI
25 Jun 2018
TL;DR: A basic power topology for a medium voltage mobile utilities support equipment based solid state transformer (MUSE-SST) with the new 10 kV SiC MOS-FETs with various challenges that comes along with it is discussed.
Abstract: A conventional transformer can withstand multiple electrical, mechanical and thermal faults which enables it to have a long lifetime. However, its inability to control the power flow through it has led researchers to look for alternate options such as the solid-state transformers. With the Silicon Carbide (SiC) semiconductor devices, it is now possible to go to high switching frequencies in medium voltage applications, which helps in reducing the overall size and weight of the transformer. The advent of medium voltage (MV) SiC devices has enabled the use of simple two-level and three-level topologies for medium voltage power transfer. This paper discusses a basic power topology for a medium voltage mobile utilities support equipment based solid state transformer (MUSE-SST) with the new 10 kV SiC MOS-FETs. A design of the MUSE-SST is presented followed by some of the practical considerations that needs to be taken, including gate driver design and heat sink configurations. Simulation results for a 100 kW, MV MUSE SST system is presented. Experimental results are provided validating the operation of these 10 kV devices in double pulse tests, buck and boost operation. This research helps in providing an overview regarding the usage of the 10 kV SiC devices in grid-interconnection and also discusses various challenges that comes along with it.

27 citations

Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this paper, an AC light dimmer topology using two voltage-controlled symmetrical switches is presented, and gate driver circuits are presented to fulfill EN55015 standard with low commutation losses.
Abstract: An AC light dimmer topology using two voltage-controlled symmetrical switches is presented. After an introduction of the silicon structure of these new engineering devices, their conduction losses are compared to today technologies. Gate driver circuits are presented to fulfill EN55015 standard with low commutation losses. The impact of the recovery current is also discussed

27 citations

Patent
08 Feb 1991
TL;DR: In this article, a floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM to reduce power consumption, size, and circuit complexity of the memory cell, and a bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor.
Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

27 citations

Journal ArticleDOI
TL;DR: The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described, which features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design.
Abstract: The analysis and design of a highly-efficient 80 V class-D power stage design in a 0.14 μm SOI-based BCD process is described. It features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip.

27 citations

Patent
27 Jul 2001
TL;DR: In this article, the authors proposed a method to translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption.
Abstract: The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver (20) adjacent thereto. The high side gate drive includes a high side gate driver logic input (HIN), a high side gate driver output (HO), a latch (22) connected between the high side gate driver logic input and the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202351
202297
2021235
2020372
2019425
2018449