Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Matrix substrate and liquid crystal display as well as projector using the same

Abstract: A liquid crystal display comprising one or more than one shift registers is characterized in that the timing of turning off the input gate of the inverter connected to the gate of the pMOS transistor of the CMOS transistor is earlier than that of the input gate of the inverter connected to the gate of the nMOS transistor of the CMOS transistor by the difference between the two MOS transistors in the time required for getting to a threshold level after turning off the input gate.

Built-in gate driver and display device having the same

Abstract: A built-in gate driver having an improved reliability and a display device having the same are provided. A transistor controlled by an output signal of a next stage is further provided and thus a node (Q) is rapidly discharged. Accordingly, the multi-output signals due to the reduced discharge of the node (Q) caused by the degradation of the transistor controlled by a node QB can be prevented. By including only one transistor for controlling the charge of the start pulse signal on the node (Q), it is possible to prevent a malfunction from occurring when the transistor connected to the clock is degraded by the periodic clock of a high state. Also, an image quality and the reliability of the gate driver can be improved.

CMOS Active Gate Driver for Closed-Loop d v /d t Control of GaN Transistors

Abstract: This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high d v /d t of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the d v /d t with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the d v /d t sequence of the switching transients. Hence, the d v /d t and d i /d t can be actively controlled separately, and the tradeoff between the d v /d t and E ON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for d v /d t active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak d v /d t from –175 to –120 V/ns for the 400 V application.

Circuit for generating driving voltages and liquid crystal display using the same

Abstract: A liquid crystal display is provided, which includes: a liquid crystal panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels including switching elements connected to the gate lines and the data lines, liquid crystal capacitors and storage capacitors connected to the switching elements; a gate driver for supplying gate voltages for driving the switching elements to the gate lines; a data driver for supplying gray voltages corresponding to applied data signals to the data lines; and a driving voltage generator for boosting a voltage according to a booster clock signal and for generating the gate voltages and a common voltage based on the boosted voltage, and the booster clock signal is synchronized with the common voltage.

Sense amplifier for a semiconductor memory device

Abstract: In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-­select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input ter­minal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increas­ing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".