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Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the heavy-ion fluence required to induce SEGR in power MOSFETs is measured as a function of the drain bias, V/sub DS/, and as a result, the SEGR-voltage threshold is abrupt.
Abstract: The heavy-ion fluence required to induce Single-Event Gate Rupture (SEGR) in power MOSFETs is measured as a function of the drain bias, V/sub DS/, and as a function of the gate bias, V/sub GS/. These experiments reveal the abrupt nature of the SEGR-voltage threshold. In addition, the concepts of cross-section, threshold, and saturation in the SEGR phenomenon are introduced. This experimental technique provides a convenient method to quantify heavy-ion effects in power MOSFETs.

26 citations

Patent
Farhad Barzegar1
26 Aug 1986
TL;DR: In this article, a gate driver circuit was proposed to reduce the noise susceptibility of a MOSFET switch by utilizing dual drive paths to apply turn-on and turn-off bias signals to the gate.
Abstract: A MOSFET gate driver circuit reduces the noise susceptibility of a MOSFET switch by utilizing dual drive paths to apply turn-on and turn-off bias signals to the gate of the MOSFET. Drive pulses are coupled to the MOSFET switch via a pulse transformer which has two serially connected secondary windings. Turn-on pulses are coupled by a diode from the first secondary to the MOSFET gate. Turn-off pulses are coupled via the second secondary to a control MOSFET which is turned on by a turn-off pulse and remains on in order to keep the gate of the MOSFET switch to a hold off voltage.

26 citations

Patent
Uryon S Davidsohn1
07 Dec 1970
TL;DR: In this article, diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFLT device as the source of the next integrally formed MOS FLT device are discussed.
Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

26 citations

Proceedings ArticleDOI
17 Mar 2013
TL;DR: In this article, the closed-loop control of diC/dt and dvCE/dt by the use of an active IGBT gate drive (AGD) is investigated on the basis of control-oriented small signal IGBT modeling and the analysis of IGBT module parasitics.
Abstract: Closed-loop IGBT switching trajectory control by means of an active IGBT gate drive (AGD) ensures an operation of the IGBT in the SOA and enables the minimization of switching delays, switching losses and EMI. In this paper the closed-loop control of diC/dt and dvCE/dt by the use of an AGD is investigated on the basis of control-oriented small signal IGBT modeling and the analysis of IGBT module parasitics. Therewith, analytical stability considerations are carried out employing root-locus plots. Furthermore, the transfer functions for different closed-loop controlled IGBT modules are analyzed in dependency of their parameter variations and parasitic inductances. A closed-loop AGD prototype is used to experimentally test, verify and comparatively evaluate the switching behavior of the different considered IGBT modules.

26 citations

Journal ArticleDOI
TL;DR: In this paper, a modulation method is proposed to completely eliminate the pulsewidth mismatch, which does not require the information of filter parameters, neither gate driver synchronization, and nor a special function block of the digital controller.
Abstract: A Grid-tied inverter utilizing wide bandgap devices can achieve higher switching frequency resulting in a power filter with reduced size and weight. However, the increased switching frequency may lead to more switching harmonics entering the electromagnetic interference (EMI) frequency range, which will increase the size of EMI filter. Interleaving paralleled converters can cancel some of the switching harmonics and reduce the size of EMI filter. However, nonideal interleaving will deteriorate the harmonic canceling effect. In this research, the nonideal effects are found to be from the small mismatch of the pulsewidth of the interleaving legs and the mismatch of the impedance between the interleaving legs. A modulation method is proposed to completely eliminate the pulsewidth mismatch. Compared with other solutions, the proposed method does not require the information of filter parameters, neither gate driver synchronization, and nor a special function block of the digital controller. The proposed modulation was implemented on a 150 MHz digital signal processor and a 100 MHz field-programmable gate array, and was experimentally verified on a 100 kW parallel coupled SiC PV inverter prototype.

26 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202351
202297
2021235
2020372
2019425
2018449