Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

A Single Voltage-Balancing Gate Driver Combined With Limiting Snubber Circuits for Series-Connected SiC MOSFETs

Abstract: Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are required to be connected in series to meet the high-voltage requirement since the blocking voltage of a single device is limited. In order to solve the voltage unbalancing problem in such a series-connection application, a single voltage-balancing gate driver combined with limiting Snubber circuits is proposed in this article. This gate driver only requires one standard driver circuit to drive two series-connected SiC MOSFETs by adding simple coupling circuits, and limiting Snubber circuits are applied for voltage balancing, and thus, low-cost, simple structure and high reliability are acquired. The analysis is given to demonstrate the working process of such a circuit structure, and the key parameters’ design and setting are focused on. In the LTspice simulation of two SiC MOSFETs in series, the proposed gate driver shows good voltage balancing performance as the power loop current increasing. Besides, the branch of series-connected SiC MOSFETs is in reliable ON- or OFF-state during steady process. Finally, the experimental results further verify the performance of proposed single voltage-balancing gate driver.

Transistor construction for low noise output driver

Abstract: A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.

Inrush limiter circuit

Abstract: A junction field effect transistor (JFET), acting as a switch, is coupled between the source and gate of a metal oxide semiconductor field effect transistor (MOSFET). A capacitor is connected in parallel with the MOSFET's “Miller capacitance” by being coupled between the gate and drain of the MOSFET in series with a current limiting resistor. When the JFET is on, it has a low impedance with zero gate voltage and forces the gate to source voltage of the MOSFET to remain near zero and, thus, the MOSFET in a high impedance state, until the capacitor charges to the supply voltage.

Electro-optical device, shift register circuit, and semiconductor device

Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.

Insulated gate thyristor with gate turn on and turn off

Abstract: An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T5) that can turn off the latched IGBT.