Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Nand cell type programmable read-only memory with common control gate driver circuit

Abstract: A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

Reverse-conducting-IGBTs — A new IGBT technology setting new benchmarks in traction converters

Abstract: In this paper the main advantages of 6.5 kV Reverse Conducting IGBTs (RC-IGBTs) compared to state-of-the-art two-chip IGBT/Diode solutions for traction applications are discussed. The experimental results show the potential of RC-IGBTs as well as the increased requirements on the gate control strategy.

Ultra low-noise charge coupled device

Abstract: Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

A 600V driver IC with new short protection in hybrid electric vehicle IGBT inverter system

Abstract: We have developed a 600V high voltage half-bridge gate driver IC used to drive large current inverters such as those used in HEVs (hybrid electric vehicles). In order to improve the robustness of short circuit operation, a new short protection circuit and a noise removal circuit were proposed. Furthermore, a reduction of the short circuit current was examined. Thus, this high voltage IC can drive almost all types of IGBT (insulated gate bipolar transistor) modules up to 600A/600V.

Video display apparatus capable of displaying video signals of a plurality of types with different specifications

Abstract: A video display apparatus comprises a video-signal processing circuit for processing an input video signal, a PLL circuit for generating a clock signal, a discrimination circuit for identifying the format of the input video signal and a specification circuit for specifying the format of video information to be displayed. In addition, the video display apparatus also includes a diver-control-signal generation circuit, a driver-control-signal switching circuit and a PLL-signal control circuit. The diver-control-signal generation circuit is used for generating control signals for controlling a gate driver and a source driver which are used for driving a display panel in accordance with the identified format of video information to be displayed. The driver-control-signal switching circuit is used for selecting control signals generated by the driver-control-signal generation circuit for controlling the gate driver and the source driver in accordance with the identified format of the input video signal and a specified display format. The PLL-signal control circuit is used for controlling the clock signal generated by the PLL circuit in accordance with the identified format of the input video signal and the specified display format.