Topic
Gate driver
About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.
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TL;DR: To achieve early detection, the IGBT gate signal behavior during turn-on transient is used and to increase the effectiveness of the detection and to tolerate the variations of input to system, adaptable thresholds have been added to the analog electronics circuit implemented.
Abstract: This paper presents the analysis and design of an electronic failure detection system applied to the insulated gate bipolar transistor (IGBT), this proposal is based on the direct measurement of behavior of the gate signal during the turn-on transient. The failures by short-circuit and open-circuit devices only are considered in this paper. To achieve early detection, the IGBT gate signal behavior during turn-on transient is used and to increase the effectiveness of the detection and to tolerate the variations of input to system, adaptable thresholds have been added to the analog electronics circuit implemented. The experimental tests are presented in order to validate the proposed fault-detection technique.
99 citations
TL;DR: A derivation of the optimum width of transistors to minimize losses in monolithic CMOS buck converters is presented and a technique called "width switching" is presented that can be integrated with the inverter chain to maintain maximum converter efficiency over a wide power range, particularly at light load.
Abstract: This paper presents a derivation of the optimum width of transistors to minimize losses in monolithic CMOS buck converters. The high optimal width requires a tapered inverter chain gate driver. A technique called "width switching" is presented. It can be integrated with the inverter chain to maintain maximum converter efficiency over a wide power range, particularly at light load. Experimental results are presented from a chip containing CMOS transistors optimized for power levels between 50 mW and 200 mW. Challenges in implementing the width-switching scheme and other applications are also discussed.
99 citations
TL;DR: An analysis, design procedure and simulation results are presented for the proposed resonant gate drive circuit, which achieves quick turn-on and turn-off transition times to reduce switching loss and conduction loss in power MOSFETS.
Abstract: In this paper, a new resonant gate-drive circuit is proposed to recover a portion of the power-MOSFET-gate energy that is typically dissipated in high-frequency converters. The proposed circuit consists of four control switches and a small resonant inductance. The current through the resonant inductance is discontinuous in order to minimize circulating-current conduction loss that is present in other methods. The proposed circuit also achieves quick turn-on and turn-off transition times to reduce switching and conduction losses in power MOSFETs. An analysis, a design procedure, and experimental results are presented for the proposed circuit. Experimental results demonstrate that the proposed driver can recover 51% of the gate energy at 5-V gate-drive voltage.
98 citations
Patent•
13 Dec 1999
TL;DR: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate as mentioned in this paper.
Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.
97 citations
06 Mar 2005
TL;DR: In this article, the effects of commons source inductance for control and sync FETs are explored in detail, and it is shown that with common source induction, minimal dead time, shoot through prevention and Cdv/dt immunity could be achieved, and significant switching loss reduction could be realized for all types of synchronous rectifications.
Abstract: Synchronous rectification is widely used in low voltage high current applications to reduce conduction loss. Common source inductance is the inductance shared by gate driver loop and main power transfer path. Minimization of common source inductance has been accepted as a common design rule for power converters using power MOSFET. In this paper, the effects of commons source inductance for control and sync FETs are explored in detail. In contrary to traditional belief, common source inductance of sync FET could provide significant benefits. With sync FET common source inductance, minimal dead time, shoot through prevention and Cdv/dt immunity could be achieved, and significant switching loss reduction could be realized for all types of synchronous rectifications.
95 citations