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Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.


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Journal ArticleDOI
TL;DR: In this article, the authors explore the challenges of implementing resonant converters using silicon carbide (SiC) power devices at high frequency: namely, the issue of high parasitic inductance packages and the ability to drive and enhance the mosfet at these frequencies.
Abstract: In this paper, we explore the challenges of implementing resonant converters using silicon carbide (SiC) power devices at high frequency: namely, the issue of high parasitic inductance packages and the ability to drive and enhance the mosfet at these frequencies. Although power circuit designers have many alternative device technologies to choose from, such as silicon and gallium nitride materials, SiC devices have several advantageous attributes especially in high power applications. As a solution, we study the device performance and parasitics of SiC mosfet s in different packaging schemes. We further offer a solution to the challenges of driving SiC devices by demonstrating a multiresonant gate driver and use this scheme to drive an SiC mosfet at 30 MHz and a SiC JFET at 13.56 MHz in a class-E inverter, achieving 85.7 $\%$ drain efficiency for the mosfet and 93.8 $\%$ for the JFET.

23 citations

Journal ArticleDOI
TL;DR: An integrated buck-type dimmable synchronous LED driver for high-brightness solid-state lighting applications and a glitch-tolerant synchronous current control (GT-SCC) scheme is proposed to regulate the average LED current.
Abstract: This paper presents an integrated buck-type dimmable synchronous LED driver for high-brightness solid-state lighting applications. A glitch-tolerant synchronous current control (GT-SCC) scheme is proposed to regulate the average LED current. The GT-SCC enables fast settling time of the LED current upon start-up or PWM dimming condition, and provides reliable operation under high dV/dt slewing during switching transitions of the LED driver. The proposed LED driver consists of a high-speed low-power HV synchronous gate driver to enable on-chip synchronous rectification with a dual-nMOS power train under different input voltages for the conduction power loss reduction. Two on-chip senseFET peak and valley current sensors are also developed to offer low-power and reliable current sensing under high input voltages. Implemented in a 0.35 $\mu$ m 50 V CMOS process, the proposed LED driver supports a wide input range from 5 V to 45 V, operates up to 4 MHz with a small-value inductor of 8.2 $\mu$ H, handles a high PWM dimming frequency of 20 kHz with a wide duty-ratio range from 0.1 to 1, and delivers an average LED current of 700 mA for driving up to 12 series-connected HB-LEDs (with the maximum output power of 26 W). The proposed LED driver achieves a peak power efficiency of 97.2% and the current deviation ${\leq}{\pm} $ 3.3% of the average LED current under different conditions. The worst-case settling time achieves 3.2 $\mu$ s that is at least 2.7 times improvement over state-of-the-art counterparts.

23 citations

Journal ArticleDOI
TL;DR: This paper presents the single channel galvanically isolated gate driver optimized for driving a normally-on silicon carbide junction field effect transistor (SiC JFET) also presented at ISSCC 2012, and further integration of supervision and control circuitry and a negative voltage regulator that regulates the entire p-substrate of the driver chip are presented.
Abstract: This paper presents the single channel galvanically isolated gate driver optimized for driving a normally-on silicon carbide junction field effect transistor (SiC JFET) also presented at ISSCC 2012 [1]. The idea of the chosen direct drive JFET concept is to switch power with a normally-on SiC JFET, using the high voltage breakdown capability of the SiC JFET and ensuring a safe normally-off behavior using a normally-off low voltage MOSFET in series. By controlling the transistor gates individually the JFET can be driven with minimum switching losses and good control. The driver makes the operation and handling of normally-on SiC JFETs as safe as normally-off switches, thereby simplifying the integration of normally-on SiC JFETs into systems like switch mode power supplies. To transfer the signal from the controller to the driver over a needed galvanic isolation of 1700 V a two chip solution with a coreless transformer arranged in one package was chosen, using a 0.6 μm BiCMOS and a 0.8 μm BCD technology. Powering of the gate driver through bootstrapping has been made possible, due to the direct drive JFET concept and the further integration of supervision and control circuitry and a negative voltage regulator that regulates the entire p-substrate of the driver chip. Tested together with the JFET in a buck converter efficiencies over 99% have been measured.

23 citations

Patent
13 Jun 2008
TL;DR: In this paper, a driver amplifier control may be provided in conjunction with power amplifier control to improve the power efficiency and/or dynamic range of the transmitter system, which may lessen the burden of digital to analog converters (DACs) in transmitter systems such as cellular transmitter systems.
Abstract: Embodiments of the invention may provide for enhancement systems and methods for a power amplifier output control system. In an example embodiment, driver amplifier control may be provided in conjunction with power amplifier control to improve the power efficiency and/or dynamic range of the transmitter system. Furthermore, control over the driver amplifier may allow for relaxed power control slope, which may lessens the burden of digital to analog converters (DACs) in transmitter systems such as cellular transmitter systems. Also, systems and methods in accordance with example embodiments of the invention may provide a less sensitive solution to operational environment variations such as temperature, battery power voltage and implementation IC process.

23 citations

Proceedings ArticleDOI
01 Oct 2007
TL;DR: A new gate drive circuit is presented that enables to reduce the switching loss on both the power MOSFET and the IGBT, and both the turn on loss and the turn off loss can be decreased simultaneously without using the conventional ZVS circuit.
Abstract: In order to increase the power density of power converters, reduction of the switching losses at a high-frequency switching condition is one of the most important issues. This paper presents a new gate drive circuit that enables to reduce the switching loss on both the power MOSFET and the IGBT. A distinctive feature of this method is that both the turn on loss and the turn off loss can be decreased simultaneously without using the conventional ZVS circuit, such as quasi-resonant adjunctive circuit. Some experimental results of the switching loss of power MOSFET and IGBT used on the buck-chopper circuit is shown and confirmed the effectiveness of the proposed circuit.

23 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202351
202297
2021235
2020372
2019425
2018449