Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Liquid crystal display device and its driving method

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption while providing two screens employing two liquid crystal display panels. SOLUTION: Video display is collectively and simultaneously presented on a main panel and a subpanel by providing a first liquid crystal display panel (the main panel) and a second liquid crystal display panel (the subpanel) having different amounts of display data and a drain driver and a gate driver on the main panel side. On a main panel PNL1 side, a source driver 52 which is provided with a timing controller (TCON) 520 and a video memory (a graphic RAM) 521 and a gate driver 51 are provided. Under the control of the controller 520, the driver 52 supplies video signals to common source lines DLm (DLs) which are connected to the panel PNL1 and a subpanel PNL2. The driver 51 respectively supplies scanning signals to gate lines GLm and GLms which are individually provided to the panels PNL1 and PNL2. COPYRIGHT: (C)2004,JPO

A Segmented Gate Driver for E-mode GaN HEMTs with Simple Driving Strength Pattern Control

Abstract: Gate overshoot voltage prevention when driving E-mode GaN-based HEMTs is essential for system reliability and EMI suppression. Active gate drivers have been demonstrated to suppress gate voltage overshoot while maintaining fast turn-on. However, they normally require complex driving patterns that are determined using trial and error approaches. In this paper, an active gate driver with an integrated pattern generator is proposed to simplify the control of the dynamic gate driving strength pattern. For best trade-off between overshoot and transition speed, the gate resistance (or gate driving strength) must remain low but with a large resistance switched in briefly during the turn-on transition period. Switch timing of the driving pattern varies with load conditions and the types of transistor. To simplify the programming of the driving pattern, the gate driving strength can be controlled by changing only one external bias resistor in the proposed design. This in turn sets the bias current of a delay chain to adjust the timing of the gate driving strength pattern. The proposed design aims to create a systematic approach to simplify the selection of the gate driving strength pattern.

Gate driver and display apparatus having the same

Abstract: A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal

Drive circuit of self-quenching-type semiconductor device

Abstract: PROBLEM TO BE SOLVED: To suppress di/dt and dV/di while preventing the increase in time delay of the switching in a voltage-controlled-type self-quenching-type semiconductor device such as an IGBT(Insulation Gate Bipolar Transistor). SOLUTION: A switching circuit 6 tums on a transistor 8 (10) based on the ON (OFF) signal of an ON/OFF signal 101 and applies a power supply 15 (16) to the gate of an IGBT 25 via a low-value gate resistor 12 (14). Then, the gate capacity of the IGBT is rapidly charged (discharged) and at the same time VGB increases (decreases), and current Ic begins to increase (decrease) with a small delay time. At this point, a voltage 106 is generated at an inductance 36 being connected between an auxiliary emitter terminal Es and a main emitter terminal Em of the IGBT 25, thus activating a one-short circuit 32 (33). A switching circuit 6 turns off the transistors 8 (10) and 7 (9) due to the one-shot output 102 (103) at this point, switches a gate resistance to 11 (13) with a larger value and relaxes the rising (trailing) speed of Ic.

A low-volume multi-phase interleaved Dc-Dc converter for high step-down applications with auto-balancing of phase currents

Abstract: This paper introduces a multi-phase interleaved dc-dc converter, targeted for high-step down applications including voltage regulator modules (VRM) for microprocessors, where low volume and high efficiency are the key priorities. The introduced architecture, reducing the voltage swing at the switching node, along with doubling the effective switching frequency of the inductor current ripple, allows reducing the size of the inductors by up to 4 times, resulting in superior dynamic regulation, while maintaining high power processing efficiency of above 90%. Along with the interleaved 2-phase operation of the introduced converter, practical implementation details, including gate driver implementation, startup, and additional features such as automatic phase current balancing, are also addressed. Experimental verifications with a 12-to-1.2 V, 10 A, 250 kHz prototype show proper functionality of the introduced converter.