Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

A High-Reliability Gate Driver Integrated in Flexible AMOLED Display by IZO TFTs

Abstract: This paper presents a new gate driver integrated by IZO thin-film transistors (TFTs) with the etch stop layer structure on the polyimide substrate, which consists of nine TFTs and two capacitors. There are several advantages for the proposed gate driver, such as simple circuitry, full-swing output, low power, and good reliability. The proposed gate driver has been successfully integrated in a flexible active matrix organic light emitting display with the resolution of 200 (RGB) $\times 600$ , in which the conventional 2T1C pixel circuit with bottom-emission structure is used. It is shown that there are no distortion and good noise-suppressed characteristics for the output signals even up to 600 stages. In addition, the proposed gate driver has a good stability, since no voltage fluctuation occurs under 720-h test. Moreover, the flexible panel works well after a 10000 times repetitive bending performed on a test bench, which is mainly composed of a programmed logic controller and dc motor. During the bending test, the minimum curvature radius of flexible panel can reach to be about 5 mm.

Design and Implementation of Multilevel Inverters for Electric Vehicles

Abstract: The efficient and compact design of multilevel inverters (MLI) motivates in various applications such as solar PV and electric vehicles (EV). This paper proposes a 53-Level multilevel inverter topology based on a switched capacitor (SC) approach. The number of levels of MLI is designed based on the cascade connection of the number of SC cells. The SC cells are cascaded for implementing 17 and 33 levels of the output voltage. The proposed structure is straightforward and easy to implement for the higher levels. As the number of active switches is less, the driver circuits are reduced. This reduces the device count, cost, and size of the MLI. The solar panels, along with a perturb and observe (P&O) algorithm, provide a stable DC voltage and is boosted over the DC link voltage using a single input and multi-output converter (SIMO). The proposed inverters are tested experimentally under dynamic load variations with sudden load disturbances. This represents an electric vehicle moving on various road conditions. A detailed comparison is made in terms of switches count, gate driver boards, sources count, the number of diodes and capacitor count, and component count factor. For the 17-level, 33-level, and 53-level MLI, simulation results are verified with experimental results, and total harmonic distortion (THD) is observed to be the same and is lower than 5% which is under IEEE standards. A hardware prototype is implemented in the laboratory and verified experimentally under dynamic load variations, whereas the simulations are done in MATLAB/Simulink.

Noise immune over current protection with inherent current limiting for switching power converter

Abstract: A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches. The circuit includes a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles; wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition where false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

Power mosfet with integrated gate resistor and diode-connected mosfet

Abstract: A power MOSFET (202) is formed in a semiconductor device (200) with a parallel combination of a shunt resistor (208) and a diode-connected MOSFET (210) between a gate input node (204) of the semiconductor device and a gate (206) of the power MOSFET. A gate (212) of the diode-connected MOSFET is connected to the gate (206) of the power MOSFET. Source and drain nodes (216, 214) of the diode-connected MOSFET are connected to a source node (218) of the power MOSFET through diodes (220). The drain node of the diode-connected MOSFET is connected to the gate input node (204) of the semiconductor device. The source node(216) of the diode-connected MOSFET is connected to the gate (206) of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode- connected MOSFET source and drain nodes (216, 214) are electrically isolated from the power MOSFET source node (218) through a pn junction.

Detection of the Conduction State of an RC-IGBT

Abstract: A circuit arrangement includes: a reverse conducting IGBT configured to allow for conducting a load current in a forward direction and in a reverse direction, the IGBT having a load current path and a gate electrode; a gate control unit connected to the gate electrode and configured to activate or deactivate the IGBT by charging or, respectively, discharging the gate electrode in accordance with a gate control signal; a gate driver unit configured to detect whether the IGBT conducts current in the forward direction or the reverse direction by sensing a gate current caused by a change of a voltage drop across the load path due to a changing of the reverse conducting IGBT into its reverse conducting state, the gate control unit further configured to deactivate the IGBT or to prevent an activation of the IGBT via its gate electrode when the gate driver unit detects that the IGBT is in its reverse conducting state