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Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.


Papers
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Patent
24 Jun 2008
TL;DR: In this article, the variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed.
Abstract: A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized.

67 citations

Proceedings ArticleDOI
04 Jun 2001
TL;DR: In this article, a vertical 600 V-50 A IGBT with reverse blocking capability is developed for the first time, which can be used as a bi-directional IGBT in combination with another reverse blocking IGBT.
Abstract: A vertical 600 V-50 A IGBT with reverse blocking capability is developed for the first time. Our measurement shows reverse blocking capability up to 900 V. This IGBT can be used as a bi-directional IGBT in combination with another reverse blocking IGBT. Bi-directional IGBTs realize the low-loss AC-AC direct conversion circuit. There is great possibility to improve the performance of the reverse blocking IGBT by utilizing the FZ-NPT-IGBT structure.

67 citations

Journal ArticleDOI
TL;DR: In this paper, the realisation of a NOR gate using SLA was reported, and the operation was based on the nonlinearity of the SLA gain and the power difference between the output logic level was > 100 µW with a 9 dB contrast.
Abstract: The authors report on the realisation of a NOR gate using SLA. The operation is based on the nonlinearity of the SLA gain. The power difference between the output logic level is > 100 µW with a 9 dB contrast.

67 citations

Proceedings ArticleDOI
18 May 2008
TL;DR: In this paper, the authors demonstrate a fully functional high voltage and high current IGBT module rated at 3300 V consisting solely of reverse conducting (RC) IGBT chips, designed in accordance with the latest Enhanced Planar and Soft Punch Through technology while incorporating an integrated freewheeling diode.
Abstract: In this paper we demonstrate a fully functional high voltage and high current IGBT module rated at 3300 V consisting solely of reverse conducting (RC) IGBT chips. The RC- IGBTs were designed in accordance with the latest Enhanced Planar and Soft Punch Through technology while incorporating an integrated freewheeling diode in the same silicon volume. Future high power IGBT modules with RC-IGBT technology will be capable of providing exceptional electrical performance for the given voltage class in terms of the maximum allowable output current capability.

66 citations

Journal ArticleDOI
TL;DR: Two integrated high-speed gate drivers to enable high-frequency operation of synchronous rectifiers in high-voltage switching power converters are presented and a dynamic timing control is developed to enable soft switching operation of the converter under different input voltages for enhancing the converter reliability.
Abstract: Two integrated high-speed gate drivers to enable high-frequency operation of synchronous rectifiers in high-voltage switching power converters are presented in this paper. The first synchronous gate driver for a CMOS power train consists of a capacitively coupled level shifter (CCLS) that offers negligible propagation delays and no static current consumption, and requires only one off-chip capacitor to enable high-side power pMOS driving capability without any external floating supply. The second synchronous gate driver consists of a low-power high-speed dynamically controlled level shifter (DCLS) with a reliability-enhanced error-suppression technique for driving a dual-nMOS power train. In addition, a dynamic timing control (DTC) is developed to generate proper dead time for power FETs in order to enable soft switching operation of the converter under different input voltages for enhancing the converter reliability. The converter power efficiency can be also improved by minimizing both switching and short-circuit power losses under high-input-voltage conditions. Implemented in a 0.5 µm 120 V CMOS process, both proposed CCLS and DCLS have demonstrated to shift up 5 V signal to 100 V and 40 V, respectively, improving the FoM by at least 10 times and 2.9 times compared to respective state-of-the-art level shifters. The DTC circuit enables proper ZVS operation in a synchronous buck converter with the CCLS-based gate driver over a wide input supply range from 40 V to 100 V, providing a converter maximum power-efficiency improvement of 11.5%.

66 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202351
202297
2021235
2020372
2019425
2018449