Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Improved two-stage DC-coupled gate driver for enhancement-mode SiC JFET

Abstract: Normally-OFF SiC VJFETs have been proved to be advantageous as a “drop-in” replacement of MOSFETs and IGBTs in a variety of applications. As this device's acceptance continues to grow, developers are investigating optimized driver methods that will yield the best possible switching performance leading to higher system efficiencies. This paper presents new results for an alternative and more optimized gate driver to the capacitive coupled driver used in past literature. Additionally switching energy measurements are documented for the 50mOhm enhancement-mode SiC VJFET in the newly optimized two-stage, DC-coupled gate driver and compared against past results obtained using the initial driver design. Specific design guidelines are included for achieving the best possible results using the two stage gate driver design presented here.

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

Abstract: High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell

Abstract: A method of making an EEPROM cell structure which includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.

Insulated gate bipolar transistor (IGBT) with a trench gate structure

Abstract: This paper describes an improved IGBT with a trench gate structure, which demonstrates a low forward voltage drop of 1.4 volts at a forward conduction current density of 200A/cm2. This device structure was fabricated using a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 8 µm. This allows for a remarkable increase of channel density and elimination of the parasitic JFET effect thus reducing the forward voltage drop significantly. A static latching current density of 2700A/cm2has been achieved in the UMOS IGBT. Two-dimensional computer simulations of the UMOS IGBT has been performed to identify the optimal cell design. This optimal design is predicted to increase the SOA current density by a factor of 4.2 over the state-of-the-art DMOS IGBT at the same forward voltage drop.

High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a silicon carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200-V silicon carbide MOSFET gate driver are presented, demonstrating the switching loss of 230 μJ at 800 V and 10 A. This represents a 20% reduction in switching losses in comparison to that of conventional gate drive methods.