Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

High-Temperature Silicon-on-Insulator Gate Driver for SiC-FET Power Modules

Abstract: Silicon Carbide (SiC) power semiconductors have shown the capability of greatly outperforming Si-based power devices. Faster switching and smaller on-state losses coupled with higher voltage blocking and temperature capabilities make SiC an attractive semiconductor for high-performance, high-power-density power modules. However, the temperature capabilities and increased power density are fully realized only when the gate driver needed to control the SiC devices is placed next to them. This requires the gate driver to successfully operate under extreme conditions with reduced or no heat sinking requirements. In addition, since SiC devices are usually connected in a half- or full-bridge configuration, the gate driver should provide electrical isolation between the high- and low-voltage sections of the driver itself. This paper presents a 225°C operable, silicon-on-insulator (SOI) high-voltage isolated gate driver IC for SiC devices. The IC was designed and fabricated in a 1 μm, partially depleted, CMOS process. The presented gate driver consists of a primary and a secondary side which are electrically isolated by the use of a transformer. The gate driver IC has been tested at a switching frequency of 200 kHz at 225°C while exhibiting a dv/dt noise immunity of at least 45 kV/μs.

An all-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages

Abstract: An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

Active Gate Driver for Improving Current Sharing Performance of Paralleled High-Power SiC MOSFET Modules

Abstract: Featuring higher switching speed and lower losses, the silicon carbide MOSFETs (SiC MOSFETs) are widely used in higher power density and higher efficiency power electronic applications as a new solution. Due to the limited current capability of a single module, more modules parallel-connected are necessary for higher power application. However, current sharing is the key obstacle. In this article, an active gate driver (AGD) for high-power SiC MOSFETs is presented to balance the currents of parallel-connected SiC MOSFET modules. The principle of the AGD is based on dynamic gate drive voltage adjustment to synchronize current edges and current slopes among parallel-connected SiC MOSFET modules automatically. Each AGD measures and controls the current of its SiC MOSFET module individually. No extra supervising control circuit is needed. In addition, the hardware and software configurations are independent of the system design and no restrictions on the number of SiC MOSFET modules connected in parallel exist. Finally, the switching performance of the AGD was experimentally verified on two parallel-connected SiC MOSFET modules in a multipulse test under constant and variable load currents. In addition, the effectiveness of AGD under different control topologies has been studied with simulation and verified using three parallel-connected SiC MOSFET modules.

Touch-control liquid crystal display background of the invention

Abstract: A liquid crystal display includes a source driver, a gate driver, a plurality of pixel units, a plurality of detecting circuits, and a decision unit. Each pixel unit includes a switch transistor and a liquid crystal capacitor. When turned on by a scan signal generated by the gate driver, the switch transistor conducts a data signal voltage generated by the source driver to the liquid crystal capacitor, to adjust alignment of liquid crystal molecules. Each detecting circuit is electrically connected to one pixel unit, and includes a first transistor, a second transistor, a third transistor and a sensor unit. The first transistor conducts a constant voltage to the sensor unit when turned on, and generates a dynamic voltage when turned off. Based on the dynamic voltage, the second transistor generates a dynamic current. The third transistor conducts the dynamic current to the decision unit when turned on. The decision unit determines the position of one detecting circuit by comparing the dynamic currents output by the plurality of detecting circuits.