Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Paralleling GaN E-HEMTs in 10kW–100kW systems

Abstract: Industry is adopting GaN HEMT in 10kW–100kW and higher power systems due to the ultra-fast switching capabilities of GaN. Paralleling GaN HEMT transistors is an appealing idea to further increase the power capability and reduce conduction losses of systems. The characteristics of E-mode GaN HEMT, such as positive temperature coefficient of RDS(ON) and a temperature independent threshold voltage, are very suitable for paralleling devices. However, the main challenge for parallel operation is thought to be the diverse parasitics of the power stage and gate driver circuits, which are very sensitive to the high di/dt and dv/dt during the switching process. In this paper, an analytic model for the switching process of paralleled GaN HEMT transistors is built to analyze the effects of parasitics and device characteristics on paralleling, and the design consideration for gate driver and layout is also presented. A half bridge power stage consisting of four high-side and four low-side 60 A / 650 V GaN HEMTs in parallel is designed to undertake 240 A / 400 V hard switching on and off. Double pulse testing results are presented to confirm GaN paralleling capability.

IGBT switching voltage transient protection circuit

Abstract: A circuit for preventing switching voltage transients from damaging the IGBT during short circuit shut off, utilizing electronic gate control which decrease the rate of fall of the gate voltage of the IGBT only when a short circuit condition is sensed, thereby avoiding any losses during normal switching operation. In a first embodiment, a considerably higher value of gate resistor is switched-in in series with the gate resistor during a short circuit condition. In a second embodiment, a considerably higher value of external capacitor is switched-in in parallel with the IGBT gate input capacitance during a short circuit condition.

Switching amplifier with MOSFET driver circuit

Abstract: A switching amplifier comprises an input terminal connected to a d.c. power supply and an output terminal connected to a load. At least one power transistor is placed in series with the input and output terminals. A PWM circuit outputs a pulse width modulated signal. An isolating driver circuit between the PWM circuit and the control terminal of the power transistor comprises a low voltage power supply; a transformer having primary and secondary windings; an oscillator for outputting a high frequency signal; means for gating the high frequency signal from the oscillator to the primary winding of the transformer in response to the pulse width modulated signal from the PWM circuit; a MOSFET; means for rectifying the voltage in the secondary winding of the transformer and for applying the rectified voltage to the gate of the MOSFET; and switching means for rapidly discharging the gate of the MOSFET when the high frequency signal is no longer gated to the transformer.

MOS gate driver circuit with analog input and variable dead time band

Abstract: A MOS gate drive (MGD) integrated circuit drives a pair of MOS gated power semiconductor devices such as are used in a half bridge circuit to drive a load in a resonant power supply circuit or to drive a gas discharge lamp in a ballast circuit. The gate drive circuit includes dead time circuitry which prevents simultaneous conduction in both MOS gated devices. The duration of the dead time is controlled in response to a feedback signal that is sensed from the output supplied to the load or the lamp. A dimming function is attained by controlling the voltage of the feedback signal.

Push-pull output buffer with gate voltage feedback loop

Abstract: A push-pull output buffer for use with an integrated circuit, such as a CMOS device, uses a driver gate voltage feedback loop to control slew rate of the driver and reduce crowbar current. The feedback loop is coupled with the driver's control gate and functions to drive the gate up to an initial, intermediate level of voltage. A delay circuit coupled between the driver control gate and the buffer input delays the delivery of a control signal that couples the driver control gate to a higher level of voltage, such that an external load connected to the buffer's output is also driven to a higher level. A one way switch circuit coupled between the delay circuit and the feedback loop prevents interference there between until the higher level of voltage is applied to the control gate.