Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

A galvanically isolated gate driver with low coupling capacitance for medium voltage SiC MOSFETs

Abstract: This paper presents a galvanically isolated gate driver system for medium voltage SiC-MOSFETs. A low common mode coupling capacity of 1 pF and good electrical insulation of the gate driver power supply are achieved by using a current-loop AC-bus power supply. The power semiconductor is protected against unintentional self-turn-on by a low resistance gate path that is active while the gate driver is not powered.

Gate drive methods for IGBTs in bridge configurations

Abstract: The insulated gate bipolar transistor (IGBT) combines the advantages of both MOS and bipolar transistor technologies into a near-ideal power semiconductor switch. Of the various application areas, the use of IGBTs in the half or full-bridge power convertor configuration is very common. Such applications have typical requirements like isolated drivers, high dv/dt stress withstand, protection against shoot-through fault, etc. This paper presents various types of gate drive circuits suitable for such situations and their relative performance under actual circuit conditions. This includes pulse-transformer circuits (where a secondary power supply is not required) for PWM control, as well as opto-isolator circuits where the secondary power supply may be derived from the inverter DC bus. Protection schemes for the IGBT that can be incorporated into the drive circuit are also discussed. >

Dual mode flyback converter and method of operating it

Abstract: A DC-DC converter includes a power switching device and a mode control logic circuit to control the power switching device and generate an ON-pulse. A flip-flop is configured to be set by the mode control logic circuit. A current mode comparator is configured to reset the flip-flop and to compare a signal based upon current flowing through the power switching device with a signal based upon an output voltage of the dual mode flyback DC-DC converter. A transformer is driven by the current mode comparator. The mode control logic circuit includes a timer starting when a gate driver control signal applied to the power switching device turns the power switching device off and configured to generate a pulse when an off time interval elapses, a zero current detector circuit configured to sense a voltage on the transformer and generate a pulse when the voltage drops below a trigger threshold, and a combinatory logic circuit configured to compare pulse signals generated by the timer and the zero current detector circuit and generate the ON-pulse based thereupon.

Dynamic RAM with non-volatile back-up storage and method of operation thereof

Abstract: A dynamic random access memory having a non-volatile back-up storage capability including a latent image capability, and method of operating the memory. Each memory cell is composed of a dynamic portion and a non-volatile portion connected to the dynamic portion. The non-volatile portion is formed of a dual gate FET, one gate of which is a floating gate. A segment of DEIS (Dual Electron Injection Structure) material is provided to control the charge of the floating gate. A capacitor couples the floating gate to the source of the dual gate FET and to the data node of the cell. The second gate of the dual gate FET can be grounded to turn off the channel of the dual gate FET independent of the charge on the floating gate during normal dynamic memory operations. To perform a non-volatile storing operation, the voltage applied to the DEIS material opposite the floating gate is taken first positive and then negative. During the positive portion of the cycle, if the data at the data node is a data 0, a positive charge is stored on the floating gate, while if the data at the data node is a data 0, a positive charge is stored on the floating gate during the negative portion of the cycle. To restore the data, a data 1 is written at the data node and the second gate of the dual gate FET transistor is pulsed to thereby allow the charge stored on the floating gate to control the conductivity of the channel of the dual gate FET. If a positive charge is stored on the floating gate, the channel conducts and discharges the data node, while if a negative charge is stored on the floating gate, the channel remains non-conductive and the charge at the data node is retained.

Power transistor driver circuit with current sensing and current overprotection and method for protecting power transistor from overcurrent

Abstract: A circuit and method for driving a power transistor device. The circuit for driving a power transistor device has a driver having an input and an output, the output coupled to a control input of the power transistor device and the input coupled to a primary control voltage source for driving the power transistor device. A current sensing device is coupled to the power transistor device for providing a signal proportional to the current in the power transistor device. An amplifier is coupled to the current sensing device for providing a substantially linear control signal proportional to the current in the power transistor device, the linear control signal being provided to the input of the driver as a secondary drive signal for driving the power transistor device when a current level in the power transistor device greater than a threshold level is detected. A detector is provided for detecting when the current in the power transistor device is greater than the threshold level. The detector is coupled to the current sensing device and to a reference level source, and provides an overcurrent signal to the driver for switching the driver from being driven by the primary control voltage source to the secondary drive signal. The secondary drive signal drives the driver so as to reduce the current level in the power transistor device. The driven power transistor device is preferably a power MOSFET or IGBT.