Topic
Gate driver
About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.
Papers published on a yearly basis
Papers
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TL;DR: In this paper, two additional capacitors are added to suppress the crosstalk in a phase-leg configuration, which hinders the increase of switching frequency and lowers the reliability of the power electronic equipment.
Abstract: Because of higher switching speed of silicon carbide MOSFET, the crosstalk in a phase-leg configuration will be more serious, which hinders the increase of switching frequency and lowers the reliability of the power electronic equipment. The displacement current of the gate–drain capacitor and the voltage drop on the common-source inductors can induce the crosstalk. In order to suppress the crosstalk, this paper proposes a novel gate driver, in which two additional capacitors are added to create the low turn-off gate impedance. With this proposed driver, the common-source parasitic inductor can be decoupled from the gate loop and the displacement current of the gate–drain capacitor can be bypassed. In addition, the operating principle and the parameters design are also analyzed. Finally, the crosstalk in the non-Kelvin package and the Kelvin package are tested by experiments, the validity of the analysis and the effectiveness for suppression the crosstalk are proved as well.
45 citations
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20 May 2018TL;DR: A novel hybrid-current-mode switching-cycle control approach has been proposed and validated on a SiC-PEBB-based modular multilevel Buck converter (MMBC) based on 1.7 kV SiC MOSFET power modules.
Abstract: This paper presents a part of the design for a power electronics building block (PEBB) based on 10 kV SiC MOSFET power module. A H-bridge PEBB system architecture is introduced at the beginning, followed by the design details of a smart gate driver. Strong noise-immunity, high driving current and effective protection circuitry have been accomplished. The design of power supply that feeds the gate drivers while providing 10 kV galvanic isolation is also shown. A resonant current bus (RCB)-based topology is proposed to supply the gate drivers, achieving both high density and low input-output capacitance of the isolation. Finally, a 10 kV laminated DC bus-bar with new layer-stacking structure is presented. Experimental results are embedded in each section to validate the PEBB performance.
45 citations
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03 Sep 1999TL;DR: In this article, the authors present a display device and an apparatus and a method for driving the display device, which includes a gate driver and a data driver for dividing the data lines into a certain number of blocks, each block having a predetermined number of data lines.
Abstract: Disclosed is a display device (e.g., a liquid crystal display), and an apparatus and a method for driving the display device. The LCD includes an LCD panel having a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and a plurality of TFTs each having a gate electrode connected to one of the gate lines and a source electrode each connected to one of the data lines; a gate driver for sequentially supplying gate drive signals to the gate lines to turn the TFTs ON; and a data driver for dividing the data lines into a certain number of blocks, each block having a predetermined number of data lines, and applying image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block. The apparatus includes the gate driver and the data driver. The method includes the steps of sequentially supplying the gate drive signals to the gate lines to turn the TFTs ON; and applying the image signals to the data lines in an (n)th block, and applying precharging voltages to the data lines in an (n+j)th block.
45 citations
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17 Jun 1999TL;DR: In this paper, a resistor is provided between the gate terminal of the power MOSFET and a gate control unit to prevent current from flowing from the drain terminal to the gate control units in an event of the breakdown of the first Zener diode group.
Abstract: A first Zener diode group, connected between drain and gate terminals of a power MOSFET, causes breakdown in response to a surge voltage applied to the drain terminal. A resistor, provided between the gate terminal of the power MOSFET and a gate control unit, prevents current from flowing from the drain terminal of the power MOSFET to the gate control unit in an event of the breakdown of the first Zener diode group. A second Zener diode group, connected between source and gate terminals of the power MOSFET, has a breakdown voltage lower than the gate withstand voltage of the power MOSFET. The second Zener diode group clamps the gate voltage against the breakdown of the first Zener diode group.
45 citations
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TL;DR: A new multilevel DC-link three-phase five-level voltage source inverter topology is introduced and a modified fundamental frequency modulation technique based on determination of switching states of inverter is developed, to generate the appropriate switching gate signals.
Abstract: A new multilevel DC-link three-phase five-level voltage source inverter topology is introduced here. A multilevel DC- link formed from single DC voltage supply and two cascaded half-bridge (CHB) power cells is connected to 12-switch three- phase bridge in such a way that the proposed inverter produces five levels in the output voltage waveform. Compared to comparable inverters, such as symmetrical CHB and hybrid multilevel inverters, the proposed topology maximises the number of voltage levels and reduces the number of utilised DC voltage supplies, switches, gate driver circuits and installation area. A modified fundamental frequency modulation technique based on determination of switching states of inverter is developed, to generate the appropriate switching gate signals. Furthermore, to validate the proposed topology, a low power prototype inverter has been built. The obtained simulation and experimental results ensure the feasibility of the suggested topology and also the compatibility of the used modulation technique.
45 citations