Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Display device and manufacturing method thereof

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a substrate, first and second signal lines formed on the substrate, a first thin film transistor connected to the first and second signal lines., a gate driver and a data driver connected to the first signal line and the second signal line, respectively, and a second thin film transistor formed in at least one of the gate driver and the data driver The first thin film transistor and the second thin film transistor include a first semiconductor and a second semiconductor, respectively, and the first semiconductor and the second semiconductor are formed at the different layers from each other.

Characterization and Analysis of an Innovative Gate Driver and Power Supplies Architecture for HF Power Devices With High dv/dt

Abstract: This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.

Current Sharing Behavior in Si IGBT and SiC MOSFET Cross-Switch Hybrid

Abstract: The cross hybrid (XS) concept has been demonstrated experimentally with 3.3-kV Si Insulated Gate Bipolar Transistor (IGBTs) and SiC MOSFETs in parallel, and used to calibrate 2D Technology Computer Aided Design simulations. The XS hybrid offers lower switching losses compared with full Si IGBTs and reduced oscillations compared with full SiC MOSFETs. The current sharing mechanism between the IGBT and the MOSFET in the XS hybrid has been elucidated, showing that under typical switching conditions, the IGBT dissipate 98% of the XS hybrid turn-OFF losses compared with the SiC MOSFET. Since the current density of the IGBT in the XS hybrid is twice of that of the full IGBT solution, it exhibits higher dynamic avalanche. These features results in stress at device and package level, thereby compromising robustness and reliability. In order to overcome such issues, we show that increasing the turn-OFF gate resistance improves current sharing in the XS hybrid by delaying the turn-OFF of the MOSFET, and thereby suppressing dynamic avalanche in the IGBT.

Characterization of a new 4.5 kV press pack SPT+ IGBT for medium voltage converters

Abstract: Recently developed IGBT press pack devices have become a competition for IGCTs in high power industrial applications. This paper presents an overview of state-of-the-art medium voltage power semiconductors with active turn-off capability. A new 85 mm, 4.5 kV, 1.2 kA press pack SPT+ IGBT and the corresponding freewheeling diode are characterized at hard switching as a function of the parameters dc-link voltage, load current, junction temperature, stray inductance and gate unit conditions.

Gate driver, and thin film transistor substrate and liquid crystal display having the same

Abstract: A gate driver for a liquid crystal display includes a shift register including a plurality of stages for outputting gate drive signals. Each of the stages includes a pull-up circuit for providing the gate drive signal to an output terminal in response to first and second clock signals, a pull-down circuit for providing a gate off signal to the output terminal, a pull-up driving circuit for driving the pull-up circuit in response to a first control signal, and a pull-down driving circuit for driving the pull-down circuit in response to a second control signal. Each of the stages includes a plurality of switching devices. A node of nodes where a signal line, through which the first clock signal, the second clock signal, the first control signal or the second control signal is applied, is electrically connected to a switching device includes at least two contacts.