Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Display device having driving circuit

Abstract: A display device of the present invention has a drain driver mounted to a display substrate and having a gate driver and a controller therein, and also has a power source mounted to a flexible printed board and supplying a power voltage to the gate driver. The wiring of a common control signal outputted from the controller and commonly used in control of the gate driver and the power source is formed on the display substrate so that the number of pads for connecting the display substrate and the flexible printed board is reduced. Thus, the construction of the flexible printed board is simplified, and the entire display device can be made compact.

Short-circuit ruggedness of high-voltage IGBTs

Abstract: The IGBT can run into different short-circuit types (SC I, SC II, SC III). Especially in SC II and III, an interaction between the gate drive unit and the IGBT takes place. A self-turn-off mechanism after short-circuit turn on can occur. Parasitic elements in the connection between the IGBT and the gate unit as well as asymmetrical wiring of devices connected in parallel are of effect to the short-circuit capability. In high-voltage IGBTs, filament formation can occur at short-circuit condition. Destructive measurements with its failure patterns and short-circuit protection methods are shown.

Driving circuit, shifting register, gate driver, array substrate and display device

Abstract: The disclosure relates to the field of liquid crystal display, and provides a driving circuit, a shifting register, a gate driver, an array substrate and a display device. The driving circuit comprises a pull-up module, a first pull-down module, a second pull-down module, a pull-up driving module, a pull-down driving module and a resetting module, wherein the first pull-down module outputs a switching-off signal to the output terminal according to a signal input from the clock retarding signal input terminal and a signal at a pull-down node; a second pull-down module, when the signal input from the signal input terminal is at a low level, outputs a switching-off signal to the pull-up node and the output terminal according to a signal input from a clock signal input terminal; wherein when the signal input from the signal input terminal is at a high level, the signal input from the clock retarding signal input terminal is also at a high level, and the signal input from the clock signal input terminal and that input from the clock retarding signal input terminal are opposite in phase. The driving circuit according to the disclosure can effectively remove the defect of the threshold voltage drifting due to the gate being applied to a bias voltage stress, and can also decrease the noise of the output voltage.

An Integrated Gate Driver with Active Delay Control Method for Series Connected SiC MOSFETs

Abstract: Series connected SiC MOSFETs technology can apply low rated voltage power device to medium or high voltage applications However, voltage unbalance problem limits its performance In this paper, an integrated gate driver with active delay control method for series connected SiC MOSFETs is presented to achieve voltage balance The main idea is to delay the drive signal for a time period to compensate its deviation between different SiC MOSFET The delay action is implemented by a delay line IC to adapt the fast switching process of SiC MOSFET The proposed gate driver provides a closed loop control for series connected SiC MOSFETs It can effectively balance the voltage without slowing down the switching speed or inducing extra losses, and the effectiveness of the proposed gate driver has been verified by experimental results

Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.