Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Cell operation methods using gate-injection for floating gate nand flash memory

Abstract: A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 04 A potential is required to be applied across the control gate Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device Devices using a bulk-tied FinFET-like structure are particularly suited to this method The method is also particularly suited for use on cells in a NAND array

High-Voltage Isolated Gate Drive Circuit for 10 kV, 100 A SiC MOSFET/JBS Power Modules

Abstract: A high-current, high-voltage-isolated gate drive circuit developed for characterization of high-voltage, high- frequency 10 kV, 100 A SiC MOSFET/JBS half-bridge power modules is presented and described. Gate driver characterization and simulation demonstrate that the circuit satisfies the gate drive requirements for the SiC power modules in applications such as the DARPA WBST-HPE solid state power substation (SSPS). These requirements include 30 kV voltage-isolation for the high-side MOSFETs, very low capacitance between the ground and floating driver sides, and 20 kHz operation. Block diagram and detailed discussion of principles of operation of the gate drive circuit are given, together with measured and simulated waveforms of performance evaluation.

Multicell battery system with individually controllable cell bypasses

Abstract: A multicell battery system includes at least two battery cells, and a selective cell bypass for each of the battery cells. Each cell bypass includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a source, a drain, and a gate, a first electrical interconnection from the MOSFET source to a first side of the battery cell, a second electrical interconnection from the MOSFET drain to a second side of the battery cell, and an activation circuit connected to the MOSFET gate. The activation circuit includes an AND gate having as one input an AC square wave signal and as a second input a selection signal, a capacitor connected to the AND gate output signal, and a cascade voltage doubling circuit having an input in communication with a second electrode of the capacitor and an output in communication with the MOSFET gate.

High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 µJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

Wide-dynamic-range amplifier with a charge-pump load and energizing circuit

Abstract: An amplifier has a first stage employing a pair of differentially connected NMOS amplifier transistors, a second stage composed of a bipolar current mirror circuit and two charge pumps. Each charge pump may be a switching voltage multiplier circuit without the conventional output capacitor. The outputs of the two charge pumps are connected, respectively, to the collector of the current-mirror output transistor and to the commonly connected sources of the NMOS amplifier transistors. Each charge pump serves as both a pulse-voltage energizing source and a load to the amplifier. The amplifier is incorporated with a high-current NMOS transistor in an integrated circuit, wherein one differential input of the amplifier is connected to the source of the driver transistor at which an external load, e.g. a motor, may be connected. The output (collector) of the differential amplifier is connected to the gate of the NMOS driver transistor so that the load current through the driver transistor is held regulated to a value proportional to the input or reference voltage that is applied to the other input of the differential amplifier. The peak pulse voltage of each charge pump is greater than the DC supply voltage from which the driver transistor and the two charge pumps are energized so that the dynamic range of both the input control voltage and the amplifier output to the gate of the NMOS driver transistor is much greater than the DC supply voltage to the integrated circuit.