Gate driver

About: Gate driver is a research topic. Over the lifetime, 7532 publications have been published within this topic receiving 75854 citations.

Power consumption of display apparatus during still image display mode

Abstract: A plurality of gate lines ( 51 ) connected to a gate driver ( 50 ) for supplying gate signals and a plurality of drain lines ( 61 ) connected to a drain driver ( 60 ) for supplying drain signals are provided on a substrate ( 10 ). Pixels ( 200 ) are formed in the regions surrounded by these lines. Each of the pixels ( 200 ) includes a TFT ( 70 ), a storing circuit ( 110 ) connected to the source ( 11 s ) of the TFT ( 70 ) for storing a digital signal, and a signal selector ( 120 ) for selecting a signal A or signal B in response to the signal stored in the storing circuit ( 110 ) and supplying the selected signal to a display electrode ( 80 ). Once a digital signal corresponding to a display image is written to the storing circuit ( 110 ) of each pixel ( 200 ), an image can be continuously displayed, even when operation of the drivers ( 50, 60 ) is stopped from the next frame, by continuing the operation of the storing circuit ( 110 ). Because the driver operation or the like can be suspended, overall power consumption can be reduced.

Sample-and-hold switch with low on resistance and reduced charge injection

Abstract: An improved sample-and-hold circuit includes a first MOSFET transmission gate connected between an analog input voltage and a storage capacitor. The first transmission gate is constructed to have low on resistance and operates for a predetermined period of time to rapidly charge the capacitor to input voltage. A second, smaller MOSFET transmission gate having reduced charge injection characteristics is connected in parallel with the first gate. The second gate is turned on coincidentally with the first gate but remains on for a short period of time after the first gate has been switched off.

Shift register and gate driver therefor

Abstract: The present invention relates to a shift register and a gate driver therefor. The shift register comprises: a first thin film transistor, of which a gate is connected to a first node, a source is connected to a clock signal terminal, and a drain is connected to an output terminal at current stage; a second thin film transistor, of which a gate is connected to a second node, a source is connected to the output terminal at current stage, and a drain is connected to a low level signal terminal; a third thin film transistor, of which a gate is connected to the first node, a source is connected to the low level signal terminal, and a drain is connected to the second node; a fourth thin film transistor, of which a gate is connected to the second node, a source is connected to the low level signal terminal, and a drain is connected to the first node; a first capacitor connected between the clock signal terminal and the second node; a discharging module connected between the clock signal terminal and the output terminal at current stage; a compensation module connected between the first node and the low level signal terminal. The present invention has the advantages of low cost, low power consumption and long life span etc, as well as the features of high stability, strong anti-interference capability and small delay etc.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Abstract: In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

Power semiconductor devices

Abstract: A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (Figure 14) for supplying a regulated output voltage. The device (3) may also be a switch in a circuit arrangement (60) (Figure 15) for supplying current to a load (L). These circuit arrangements (50, 60) include a terminal (Vcc, VF) for applying a supplied fixed potential to an electrode (G311) for the first gates (G31) and a gate driver circuit (573, 673) for applying modulating potential to an electrode (G321) for the second gates (G32).