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Showing papers on "Gate oxide published in 1969"


Patent
22 Jul 1969
TL;DR: In this article, a polycrystalline semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source or drain regions.
Abstract: Insulated Gate Field Effect Transistor employing a polycrystalline semiconductor surface layer, one strip of which serves as the gate electrode of the IGFET, and another strip of which may serve as a resistor. The semiconductor surface layer is employed as a mask for the diffusion of the source and drain regions, thereby insuring automatic alignment between the gate electrode and the source and drain regions.

64 citations


Journal ArticleDOI
P. Balk1, J.M. Eldridge
01 Sep 1969
TL;DR: In this article, a structural model is presented to account for the polarization and the Na+trapping behavior of the phosphosilicate glass (PSG) films, and detailed knowledge of the behavior of PSG layers permits prediction of the threshold stability of P 2 O 5 -treated FET devices.
Abstract: The threshold voltage of MOSFET devices can be effectively stabilized from changes due to field-assisted motion of Na+in the gate oxide by the addition of a phosphosilicate glass (PSG) layer. The effectiveness of the glass for this purpose is markedly enhanced by increasing the P 2 O 5 concentration of the PSG. However, polarization of the PSG layer can, in turn, cause an appreciable instability of the threshold voltage. It is shown that detailed knowledge of the behavior of PSG layers permits prediction of the threshold stability of P 2 O 5 -treated FET devices. Thus, threshold stability can be maintained to within 0.1 V/1000 A under device operating conditions by making a proper compromise on PSG thickness and P 2 O 5 concentration. Such stabilizing films offer satisfactory protection against realistic Na+contamination levels. Quantitative data on these phenomena are presented, and a simple structural model is given to account for the polarization and the Na+trapping behavior of the films. The formation of PSG films by doping of SiO 2 with P 2 O 5 at elevated temperatures is discussed.

62 citations


Journal ArticleDOI
TL;DR: In this article, the mobility and density of free carriers in surface channels have been obtained from conductivity and Hall measurements performed on large experimental silicon MOST's, with various crystallographic orientations.
Abstract: The mobility and density of free carriers in surface channels have been obtained from conductivity and Hall measurements performed on large experimental silicon MOST's. Uniform n- and p-type channels, with various crystallographic orientations have been studied over a range of temperatures, gate biases, and reverse biases between the channel and substrate. No trapping of induced carriers has been observed when the gate voltage is more than a few volts above threshold. The mobility of free carriers is very small at threshold. It increases rapidly with gate voltage and shows a maximum of about 1 3 or 1 2 of its bulk value, at gate voltages corresponding to free carrier densities of about 2–7 × 1011 carriers/cm2. At larger gate voltages the mobility shows a slow decrease. The mobility is also affected by bias between channel and substrate. A hysteresis in channel conductance is observed at room temperature. It is shown that a hysteresis in carrier mobility contributes appreciably to this effect. Finally, it is demonstrated by means of an example that the variations of mobility with gate and substrate bias have an appreciable influence on the drain characteristics of MOST's.

56 citations


Patent
30 Sep 1969
TL;DR: The threshold voltage of an IGFET is precisely controlled by the introduction of a quantity of dopants into the gate and channel region by exposure to an energetic ion beam as mentioned in this paper, which is the same as the effect described in this paper.
Abstract: The threshold voltage of an IGFET is precisely controlled by the introduction of a quantity of dopants into the gate and channel region by exposure to an energetic ion beam.

24 citations


Patent
27 Mar 1969
TL;DR: In this paper, a single gate field effect transistor with an isolating mesa formed from a layer of semi-conductor material provided on a substrate surface and which exhibits bulk negative resistance instabilities above a critical electric field strength is described.
Abstract: A single gate field-effect transistor including a semi-insulating substrate for providing a one-sided device geometry, an isolating mesa formed from a layer of semi-conductor material provided on a substrate surface and which exhibits bulk negative resistance instabilities above a critical electric field strength, an extended gate structure provided in a gate region of the mesa, source and drain structures provided on the mesa at opposite sides of the gate structure, and electrical leads connected respectively to the gate, source and drain structures. The process for making the transistor, a multichannel (interdigitated structure) version, and a closed geometry (without mesa) version are also detailed.

22 citations


Journal ArticleDOI
TL;DR: In this paper, it was shown that the damage due to ionizing radiation is substantially different if chromium is added to the gate oxide of metaloxide-semiconductor (MOS) transistors.
Abstract: Detailed studies of radiation damage in metaloxide-semiconductor (MOS) transistors show that the damage due to ionizing radiation is substantially different if chromium is added to the gate oxide. Devices with chromium consistently show smaller gate threshold shifts (due to positive charge storage in the gate oxide) when irradiated with zero or negative gate bias; they also show smaller increases in interface state density. The generation of interface states by radiation is also bias dependent in chromium MOS devices. Another difference between devices with conventional and chromium-doped oxides is the lower rate of thermal annealing when chromium is used. An extended anneal at 350°C is required to remove radiation damage from these devices. A considerable degree of control over ionization damage is thus obtained by chromium doping, and it appears this control can be used to improve radiation hardness of MOS transistors.

15 citations


Patent
C Benyon1, D Liebowitz1
11 Apr 1969
TL;DR: An electroacoustic semiconductor device, comprising a direct-coupled piezoelectric transducer with interdigitated electrodes, and an insulated gate field effect transistor fabricated on a layer of semiconductor material having a surface insulating coating, a part of which serves as the gate insulator of the transistor as discussed by the authors.
Abstract: An electroacoustic semiconductor device, comprising a direct-coupled piezoelectric transducer with interdigitated electrodes, and an insulated gate field-effect transistor fabricated on a layer of semiconductor material having a surface insulating coating, a part of which serves as the gate insulator of the transistor. An input signal applied to the interdigitated electrodes causes the transducer to launch a surface acoustic wave along the insulating coating, with a resultant change in gate electrode insulator thickness, thus controlling current flow between source and drain electrodes.

12 citations


Patent
29 Aug 1969
TL;DR: In this article, a self-aligning gate region comprising a noble metal-silicon-oxygen alloy serves as a mask for the source and drain diffusions and serves as gate electrode.
Abstract: A technique for the fabrication of a semiconductor device of the field-effect transistor-type involves a processing sequence wherein a self-aligning gate region comprising a noble metal-silicon-oxygen alloy serves as a mask for the source and drain diffusions and serves as gate electrode.

12 citations


Patent
24 Oct 1969
TL;DR: In this article, a field effect transistor with two overlapping insulated gates, the first gate being of silicon and extending only partially over the channel region between the source and drain, with the second gate being superimposed over the first one so as to cover the channel regions at least where not covered by the first.
Abstract: A field-effect transistor having two overlapping insulated gates, the first gate being of silicon and extending only partially over the channel region between the source and drain with the second gate being superimposed over the first gate so as to cover the channel region at least where not covered by the first gate and being insulated from the first gate by silicon oxide formed from the first gate.

10 citations


Journal ArticleDOI
Paul Richman1
TL;DR: In this paper, the authors used selective gold-doping techniques to achieve enhancement-type characteristics for both n-and p-channel MOSFETs on high-resistivity π substrates.
Abstract: p -Channel enhancement mode MOS field-effect transistors have been fabricated on high-resistivity p -type (π) silicon substrates. A high off-state impedance can be achieved with zero gate voltage if the substrate resistivity is sufficiently high so that the p + π low-high junctions formed by the diffusion of the drain and source regions exhibit the desired rectifying characteristics. n -channel MOSFETs can also be fabricated on these high-resistivity π substrates. While the n -channel devices usually exhibit depletion mode characteristics, both n - and p -channel enhancement type MOSFETs can be simultaneously fabricated on a single substrate if Al 2 O 3 -SiO 2 gate insulating layers are used and if Q SS is kept sufficiently small. Selective gold-doping techniques can also be employed to achieve enhancement-type characteristics for both n - and p -channel devices. The channel lengths must be sufficiently large to eliminate SCL current flow from drain to source with zero gate voltage. By using techniques such as beam-lead interconnections or dielectric isolation, complementary MOS integrated circuits can be fabricated on a single substrate and only two diffusions are required. Additional advantages of this approach include extremely high carrier mobilities, very low threshold voltages for both units, and negligible variation of MOSFET characteristics with reverse substrate bias.

10 citations


Journal ArticleDOI
A. Waxman1, G. Mark1
TL;DR: In this paper, the use of this oxide as a gate insulator results in a two-orders-of-magnitude reduction in surface state density at the Al 2 O 3 CdSe improvement in electrical stability.
Abstract: AlAl 2 O 3 CdSe thin-film transistors have been fabricated that show significant improvement in electrical stability over previous devices reported. This improvement is shown to be due to the use of Al 2 O 3 formed by plasma-anodization in a d.c. O 2 glow discharge. The use of this oxide as a gate insulator results in a two-orders-of-magnitude reduction in surface state density at the Al 2 O 3 CdSe improvement in electrical stability. Interface state densities are typically found to be less than 5 × 10 10 states/cm 2 - eV . Transistors using Al 2 O 3 have been bias-temperature tested at room temperature and up to 75°C. No shift in threshold voltage is presently observed at 75°C with gate oxide fields of 1 × 10 6 V / cm . The use of Al 2 O 3 , while resulting in improved electrical stability, has not resulted in any loss of device performance. Thin-film transistors with gain-bandwidth product of 20 MHz and gate breakdown strengths of 7 × 10 6 V/cm are obtainable. Gate threshold voltages are typically 0−0.5 V. The effects of processing steps and the reproducibility of the transistors fabrication procedure have been studied. Through the use of post-deposition hydrogen annealing, excellent reproducibility in device characteristics has been achieved. Variations in transistor characteristics across a substrate are typically less than 10 per cent, while variation from substrate to substrate is also significantly reduced. The reduction is attributed to the low interface state density and the effects of annealing on oxide charge and CdSe resistivity.

Patent
15 May 1969
TL;DR: In this article, a MIS FET is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.
Abstract: An MIS FET device and method of making the same wherein a device of nominal topology is made capable of sustaining drain to source potentials substantially higher than the normal breakdown potentials of prior art devices. The present invention is constructed with linearly graded PN junctions and the diffusion profile, as related to the geometry of the gate, is such that the junction depletion layer will extend into the drain region to a point under the thick field oxide so that a critical electric field is not produced in the thin gate oxide causing rupture thereof.

Patent
Johannes A Van Nielen1
09 Jun 1969
TL;DR: An insulated gate field effect transistor (FGET) as mentioned in this paper is an FET with a decoupling capacitor between the gate and the substrate, which can be used as a decouple capacitor.
Abstract: An insulated gate field-effect transistor having a decoupling capacitor between the gate and substrate.

Patent
Karsten E Drangeid1
12 Dec 1969
TL;DR: In this article, a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel is described, and a solid-state delay line is disclosed, where two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode.
Abstract: A solid-state delay line is disclosed which includes a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel. Two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode, respectively, and cause currents to be adjusted such that the voltage drops per unit length in the semiconductor channel and in the gate electrode are equal. A uniform thickness of the charge carrier variation zone, i.e., a depletion zone or an enhancement zone, is obtained in the semiconductor channel and the delay of signals propagating through the semiconductor channel is proportional to the length of the extended gate electrode.

Patent
17 Apr 1969
TL;DR: In this paper, a method of making a field effect transistor with an accurately aligned gate by forming the source and drain regions from a doped layer on the substrate surface is described.
Abstract: Disclosed is a method of making a field effect transistor with an accurately aligned gate by forming the source and drain regions from a doped layer on the substrate surface. The resulting transistor has reduced internal capacitance and improved speed characteristics.

Patent
18 Sep 1969
TL;DR: In this article, an insulated gate field effect transistor (IGFET) is fabricated by diffusing into a semiconductor substrate the impurities required to produce the channel, source and drain, exposing the substrate by etching away any remaining masking layer.
Abstract: An insulated gate field effect transistor having a glass gate insulator is fabricated by diffusing into a semiconductor substrate the impurities required to produce the channel, source and drain, exposing the substrate by etching away any remaining masking layer, forming a gate insulator of thin film ion impermeable glass on the exposed substrate and then metalizing and packaging the resulting device. Advantageously, the thin glass film is also used as a passivating layer. IGFET''S fabricated in this manner are significantly more resistant to contamination than are prior art devices using oxide insulated gates and passivating layers. As a consequence they are more economical to fabricate and more reliable in operation.

Patent
31 Jan 1969
TL;DR: In this article, a resonant gate transistor is provided with a gate electrode with means to bias the gate so that off detectors such as P-channel MOSFETs can be employed, such detectors being more compatible with NPN bipolar transistors for integration than normally on N-channel detectors.
Abstract: A resonant gate transistor is provided with a gate electrode with means to bias the gate so that normally off detectors such as P-channel MOSFETs can be employed, such detectors being more compatible with NPN bipolar transistors for integration than normally on N-channel detectors. The gate electrode is preferably biased by a floating diode of very small capacitance so as to avoid charge leakage and reduced gain. The gate electrode permits large area electrostatic coupling with the vibratory member.

Journal ArticleDOI
P.S. Rao1
TL;DR: In this paper, the effect of the substrate on the gate and drain noise parameters in MOSFETs is calculated up to first order terms in jw, under the assumption that the channel has thermal noise.
Abstract: The effect of the substrate on the gate and drain noise parameters in MOSFETs is calculated up to first order terms in jw, under the assumption that the channel has thermal noise. It is shown that the substrate doping has little influence on the gate noise, i g 2 , and on the cross correlation between gate and drain noise i g i d ∗ . The theory cannot explain Halladay and van der Ziel's data. Therefore a non-thermal noise source must be operating in the channel.

Journal ArticleDOI
TL;DR: The Silicon Gate Technology as discussed by the authors is a new approach to fabricating insulated gate field effect transistor circuits, in which the metal gate electrode is replaced by a doped, silicon electrode, and the work function difference between the gate electrode and semiconductor bulk will now be determined by the doping of the gate electrodes.
Abstract: The Silicon Gate Technology is a new approach to fabricating insulated gate field effect transistor circuits, in which the metal gate electrode is replaced by a doped, silicon electrode. The work function difference between the gate electrode and semiconductor bulk will now be determined by the doping of the gate electrode. This leads to normally off p-channel devices with threshold voltages typically between 1.1 v and 2.5 v on material with 1000A gate oxide. It is a self-aligned gate structure and has a buried-gate electrode which allows crossover of gate regions and closer spacing of source-drain contact. The fabrication needs 4 masking steps and was found to be compatible with existing planar technology.

Patent
19 May 1969
TL;DR: In this paper, a noble metal-silicon-oxygen alloy is used as a passivation type layer on a silicon dioxide layer located on one surface of a silicon substrate or device.
Abstract: This disclosure relates to the formation of stable semiconductor devices by using a noble metal-silicon-oxygen alloy as a passivation type layer on a silicon dioxide layer located on one surface of a silicon substrate or device. The noble metalsilicon-oxygen alloy is deposited onto the semiconductor substrate surface during an anodization process preferably using a hydrogen peroxide solution containing from about 30 percent to about 0.1 percent hydrogen peroxide by volume in water. The anodization process serves to remove positive ion impurities from the silicon-silicon dioxide surface area which adversely affects the stability of the device. In one example, the noble metalsilicon-oxygen alloy is deposited primarily as a conductive layer while in another example, the noble metal-silicon-oxygen alloy is deposited as an insulating layer. For either example, the noble metal-silicon-oxygen alloy serves as a barrier to prevent impurities such as positive sodium ions from reaching the area of the silicon-silicon dioxide interface. This noble metal-siliconoxygen layer is useful in various types of semiconductor devices including bipolar and unipolar devices.

Proceedings ArticleDOI
01 Jan 1969
TL;DR: In this article, the authors describe gate shorts caused by electrical breakdown of the gate oxide are a major yield and reliability problem for MOS transistors and integrated circuits and use diffused resistors with breakdown voltages of about 50 V to protect the gate from high voltage transients or discharges.
Abstract: Gate shorts caused by electrical breakdown of the gate oxide are a major yield and reliability problem for MOS transistors and integrated circuits. Generally, diodes or diffused resistors with breakdown voltages of about 50 V are used to protect the gate from high voltage transients or discharges.

Patent
Else Kooi1
21 May 1969
TL;DR: In this paper, an insulated gate field effect transistor (IGFET) is described with a thin insulator under the gate and a thick insulator between the source and drain connections.
Abstract: An insulated gate field effect transistor is described having a thin insulator under the gate and a thick insulator under source and drain connections. The insulator over the source and drain is impurity doped, which impurity is diffused into the semiconductor body to form the source and drain. However, the insulator under the gate is a mask against diffusion of the said impurity.

Patent
23 Apr 1969
TL;DR: In this paper, an insulated gate field effect transistor is described in which an additional region of the opposite type conductivity is inset in the source or drain regions and connected to the gate.
Abstract: An insulated gate field-effect transistor is described in which an additional region of the opposite type conductivity is inset in the source or drain regions and connected to the gate. The additional junction thereby formed is reverse biased during operation. When inset in the drain, the reverse-biased junction provides additional gate-drain capacitance for a Miller integrator circuit, whereas when inset in the source, the additional junction can act as a safety diode between the gate and source. The low breakdown voltage of the additional junction due to the high-impurity content of the regions increases the protection afforded by the safety diode.

Patent
Finis E Gentry1
12 Dec 1969
TL;DR: In this paper, an SCR is formed with a diffused region interposed between the gate and adjacent edge of the emitter layer to increase the lateral resistance offered to the gate signal.
Abstract: An SCR is formed with a diffused region interposed between the gate and adjacent edge of the emitter layer to increase the lateral resistance offered to the gate signal and thereby assure more uniform conduction of the gate signal. The gate metallization shorts the adjacent edge of the junction associated with the diffused region, and the shorted edge is substantially uniformly spaced from the adjacent edge of the emitter layer so that the lateral resistance to signal current is substantially uniformly distributed.

Patent
10 Feb 1969
TL;DR: In this paper, an insulated gate field effect transistor was described with a titanium dioxide surface layer over the usual insulating layer to interrupt surface charge migration between its source and drain, and the transistor was used for the first time.
Abstract: An insulated gate field effect transistor is described having a titanium dioxide surface layer over the usual insulating layer to interrupt surface charge migration between its source and drain.

Patent
28 Nov 1969
TL;DR: In this article, the authors present an enhancement-type Insulated Gate Field Effect Transistor (IGFET) which comprises a substrate entirely of one conductivity type having at the surface thereof source and drain regions of the opposite conductivity types, and a conductive gate or gates, overlying but insulated from the substrate.
Abstract: Time delay devices, each an enhancement-type Insulated Gate Field Effect Transistor (IGFET) which comprises (1) a substrate entirely of one conductivity type having at the surface thereof source and drain regions of the opposite conductivity type, and (2) a conductive gate or gates, overlying but insulated from said substrate. If the device includes one gate, it may overlie either (a) part of the controlled region of the substrate between the source and drain regions, or (b) portions of the substrate remote from said controlled region. If the device includes plural gates, one gate has a floating potential and overlies the controlled region of the substrate, and the other biased gate overlies a portion of the substrate remote from said controlled region. When the source-drain circuit is biased conventionally, the application of a potential of the proper polarity to the gate will cause a charge to migrate slowly from the gate over the surface of the IGFET. As the charge covers the controlled region, it induces a change in conductivity type in the surface of the portion of the controlled region which it covers, thereby causing the source-drain circuit to become fully conductive after a predetermined delay. The delay is dependent upon ambient moisture and temperature, gate configuration, and resistivity of the IGFET''s surface oxide layer. In one type of such devices, where generally a single gate bridges the controlled region of the substrate, a source-drain current appears immediately when a potential is applied to the gate; this current rises gradually to a saturation value. In another type of such devices, where generally a single gate does not bridge the controlled region, or where plural gates (with one floating) are used, the source-drain current begins only a given time after the application of a potential to the gate but then increases relatively rapidly to saturation value.

Journal ArticleDOI
M. Dierckens1
TL;DR: The expressions for drain current, mutual transconductance and output conductance of a junction f.t. below pinchoff, given by Bockemuehl, are generalised to structures where the gate doping profile is arbitrary and where the depletion region penetrates also in the gate region as discussed by the authors.
Abstract: The expressions for drain current, mutual transconductance and output conductance of a junction f.e.t. below pinchoff, given by Bockemuehl, are generalised to structures where the gate doping profile is arbitrary and where the depletion region penetrates also in the gate region.

Patent
Rijkent Jan Nienhuis1
13 Oct 1969
TL;DR: In this article, a junction field effect transistor (JFET) is described for power applications, which comprises interdigital source and drain contacts and a surface gate electrode connected at its ends to a substrate gate.
Abstract: A junction field effect transistor adapted for power applications is described. It comprises interdigital source and drain contacts and a surface gate electrode connected at its ends to a substrate gate. To reduce the gate resistance, plural zones are provided which extend through the channel interconnecting the surface gate with the substrate gate regions. The interconnecting zones may be in the form of columns or strips.