Showing papers on "Gate oxide published in 1970"

A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide

Abstract: Results of an experimental study are reported of a new instability found in p- and n-channel MOS transistors. This phenomenon is that when a higher voltage in an excess of a brakdown voltage is applied to the drain electrode the breakdown voltage drifts to a higher value and the drain current also increases. The origin of this instability is investigated by extensive measurements and analyses of the electrical characteristics of the transistors. It is concluded that 1) the semiconductor surface near the drain becomes p-like in the p-channel transistors and n-like in the n-channel transistors and thus the active channel length is shortened, 2) this is caused by charging of the gate oxide due to injection of electrons or holes generated during the drain avalanche breakdown, and 3) electron and hole injection is much affected by electric field across the oxide over the drain junction.

Floating gate transistor and method for charging and discharging same

Abstract: A floating gate transistor comprising a floating silicon or metal gate in a field effect transistor which is particularly useful in a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO2 is charged by transferring charged particles (i.e., electrons) across the insulation from the substrate during an avalanche (breakdown) condition in the source or drain junctions of the transistor.

Integrated circuit structure and method for making integrated circuit structure

Abstract: In connection with the fabrication of an integrated circuit, a method for simultaneously completing the formation of a contact, an interconnect, a gate and a source or drain is disclosed. An integrated circuit field effect structure wherein a diffused silicon area is connected directly to a polysilicon member by conductive silicon and more specifically the source or drain of one device is directly and continuously connected to the gate of an adjacent device by a conductive silicon member.

Field effect semiconductor device with memory function

Abstract: A field effect transistor is provided with a gate assembly comprising a sandwich of a layer of silicon oxide with excess silicon between two insulating films of appropriate thickness for the entrapment of charge carriers in the silicon-rich silicon oxide layer. Such entrapment provides the transistor with information storage capabilities in which information can be stored for a long time and readily erased or modified.

Fabrication of insulated gate field-effect transistors involving ion implantation

Abstract: An insulated gate field-effect transistor is made which utilizes both Schottky barrier connections and ion-implanted zones. The resultant structure incorporates source and drain zones, which are formed by ion implantation and whose spacing is fixed by the gate electrode, and source and drain electrodes which make ohmic connection to the implanted source and drain zones and rectifying connections to unimplanted material.

Complementary insulated gate field effect devices

Abstract: A complementary pair of insulated gate field effect transistors is fabricated in a monocrystalline silicon wafer. The method features the use of doped-oxide diffusion sources, self-aligned, passivated-gate electrodes, and the concurrent diffusion of the source and the drain regions for both the n-channel device and the p-channel device in a single step.

Diffusion guarded metal-oxide-silicon field effect transistors

Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

Complementary metal oxide semiconductor gate protection diode

Abstract: Gate protection is given to a complementary metal oxide semiconductor (CMOS) devices against excessive input voltage transients. An input diode which has a lower breakdown voltage than the gate oxide is attached to the input terminal to protect the gate oxide. The input protect diode is formed by diffusing an N+ region which overlaps both a P tube and an N substrate. The diffusion concentrations between the various regions determine the breakdown voltage of the protection diode. The overlapping relationship of the N+ diffusion over the P- tub and N substrate creates a structure which prevents parasitic NPN action.

Methods of manufacturing insulated gate field effect transistors

Abstract: A method of making an IGFET by implantation techniques is described. The method features provision of the source and drain contact metal on the semiconductor surface and an adjoining insulator, provision of a gate electrode structure which will mask ions, and then ion bombardment under such conditions that the ions do not penetrate the gate electrode structure thereby defining a channel precisely aligned with the gate, but ions do penetrate the adjacent structure to form in the underlying semiconductor source and drain surface regions wholly defined by the implantation and whose p-n junctions terminate under the insulator. Upon completion, the source and drain contacts for the source and drain regions are automatically established. Various methods are described for controlling the locations where the ions are masked or are permitted to penetrate into the semiconductor.

Insulated gate field-effect device and method of fabrication

Abstract: An insulated gate field-effect transistor is fabricated to include an improved insulation layer comprising a film of silicon dioxide covered with a film of silicon nitride. The method of fabrication includes the thermal oxidation of a semiconductor silicon surface in a ''''reducing'''' atomsphere. The use of hydrogen as a carrier gas for oxygen provides a thermally grown, pinholefree oxide film having improved stability under conditions of heat cycling and electrical bias. The process permits a control of oxidation rate by adjusting the oxygen content of the gaseous mixture, rather than by the control of temperature. Best device characteristics are obtained by proceeding immediately with the vapor deposition of silicon nitride on the oxide, as a substantially continuous operation in the same reactor.

Self-aligned gate field effect transistor with schottky barrier drain and source

Abstract: A LOW PARASITIC CAPACITANCE FIELD EFFECT TRANSISTOR IS FABRICATED BY THE UTILIZATION OF A SELF-ALIGNING GATE TECHNIQUE. A METAL GATE IS FORMED AND THEN, EMPLOYING THE GATE AS A MASK, LOW TEMPERATURE SCHOTTKY BARRIER SOURCE AND DRAIN JUNCTIONS ARE FORMED. THE TECHNIQUE IS PARTICULARLY USEFUL IN THE FABRICATION OF THE FIELD EFFECT TRNASISTOR AS AN ELEMENT OF A LARGE INTEGRATED CIRCUIT WHERE MANY SUCH ALIGNMENTS MUST BE MADE SIMULTANTEOUSLY. D R A W I N G

Electronic memory circuit employing semiconductor memory elements and a method for writing to the memory element

Abstract: Data is written into a memory storage device by applying a negative voltage to the gate electrode of an MIS-type transistor, and a positive voltage to at least one of the drain and source of that transistor. The voltage difference between the gate and the source or drain exceeds a critical voltage so that electrons are injected and trapped in the gate film. Also disclosed is a memory matrix in which a plurality of MIS transistors are arranged in a matrix array and have their gate and source-drain electrodes connected to row-and-column drive lines.

Potential, field and carrier distribution in the channel of junction field-effect transistors

Abstract: The operation mechanism of field-effect transistors (FET) was investigated by the measurements of the potential distribution in the channel using a tungsten needle as a probe in alloyed junction type FET in operation. The field distribution and the free carrier distribution were obtained as the first and the second derivative of the measured potential distribution. It is clear that, before the current saturation, from the source to the drain the electrically neutral channel exists. In this region the ionized impurity density and the carrier density are equal and the field toward the gate can be neglected. Contrary to this, in the channel at the drain side after the current saturation, the space charge layer extending from the gates reaches near the channel centre and the field to the gate direction becomes extremely high. In this region, an effective channel is formed in which the free carriers decrease toward the gate. At the centre of the effective channel, the electrical neutrality almost holds. Almost all of the voltage after the current saturation are spent in this region which is independent of the source side. In this short high field region, the field seems to be even in the velocity saturation region ( E >1·5×10 4 V/cm) of the carriers. The highest field region is rather outside of the gates. The potential and the carrier distribution in the channel at the drain side show a fairly good agreement with the theoretical calculation analysed in this paper.

Semiconductor device comprising an insulated gate field effect transistor and method of manufacturing the same

Abstract: Method of making an insulated gate field effect transistor is described in which the surface of a silicon semiconductor is covered in whole or in part with a layer of a masking material which masks against oxidation, such as silicon nitride. Areas of the silicon surface are exposed for the source and drain regions, leaving the oxidation mask over the future channel. When the source and drain regions have been made, as for example by diffusion, the device is subjected to oxidation, causing the growth of a thick oxide which sinks into the silicon surface where it is not masked by the oxidation mask. Among the advantages obtained are fewer precise masking steps, a flatter device surface, and reduced gate overlap of the source and drain.

Self-aligned gate field effect transistor and method of preparing

Abstract: This disclosure relates to a high frequency field effect transistor with and accurately aligned gate contact disposed between source and drain contacts. The device consists of a substrate having a substantially flat upper surface, a layer of lightly doped semiconductor material having its bottom surface disposed on the surface of the substrate and a metal layer disposed on the upper surface of the layer of semiconductor material. An aperture is formed through the metal layer into the layer of semiconductor material. The gate contact is disposed within the aperture while the metal layer around the periphery of the aperture form the source and drain contacts.

Fabrication of an insulated gate field effect transistor device

Abstract: An insulated gate field effect transistor is fabricated by a sequence of steps beginning with the growth and patterning of a thick oxide layer on an n-type silicon wafer. A thin gate-dielectric film is then formed on the exposed silicon surface, followed by deposition and patterning of the gate electrode thereon. The excess gate dielectric is removed, using the electrode as an etch resistant mask, and the wafer is then covered with a boron-doped silane oxide diffusion source for the formation of p-type source and drain regions. The resulting self-aligned and passivated-gate structure is then provided with ohmic contacts to complete the device.

Three masking step process for fabricating insulated gate field effect transistors

Abstract: A three resist-masking step process produces lower cost monolithic integrated circuit insulated gate field effect transistors with improved electrical characteristics. To fabricate a metal-nitride-oxide-silicon device, layers of grown oxide, silicon nitride, and field oxide are deposited on a wafer, and the first mask facilitates etching of source and drain openings. After depositing activator impurity and glass, and diffusing, the second mask is used in simultaneously etching contact holes and a gate opening using the silicon nitride as an etch stop. The third mask delineates the contact metallizations.

Protective circuit for input circuit of junction type field effect transistor

Abstract: In a protective circuit for input circuit of a junction type field effect transistor, a plurality of gate electrodes are provided for the transistor, an input protective resistor is connected between a signal input terminal and an input side gate electrode and the other gate electrode is connected to the source electrode of the field effect transistor. The protective resistor functions to protect the field effect transistor against excessive forward voltage by passing current between the input side gate electrode and the source electrode and against excessive reverse voltage by passing current between the other gate electrode and the input side gate electrode.

Insulated gate type field effect semiconductor device having narrow channel and method of fabricating same

Abstract: A method for fabricating an integrated gate field effect transistor is disclosed wherein an induced conduction region is formed between the source and drain regions by the application of a suitable potential between the gate electrode and substrate. The surface of the device is irradiated by a high-energy beam, thereby to form a narrow channel in the conduction region which defines the gate channel of the field effect transistor.

On the gate current and noise behavior in pinched-off silicon junction field-effect transistors

Abstract: An exponential relation between the gate current of the silicon junction FET and the drain applied voltage is obtained experimentally. It is found that the noise enhancement and input impedance decrease of this device starts at a point corresponding to the appearance of the gate floating potential which is related to the gate current.

Insulated gate field-effect transistor with variable gain

Abstract: An insulated gate field-effect transistor comprising a source and drain which define the ends of a plurality of current carrying paths of controllable conductivity, and a gate separated from the current paths by an insulator. The width of the gate is less than the length of some of the current paths below it and is spaced from the drain in a direction parallel to the current paths with a spacing that varies along the length of the drain; and, therefore, different drain voltages are required to achieve conduction along different ones of the current-carrying paths for any given gate voltage. This permits varying the drain voltage to achieve a variable gain.

Field effect transistor modulator circuit

Abstract: A modulator circuit employing two dual gate field effect transistors. A carrier signal is applied to one gate of each transistor in a push-pull arrangement. A modulating signal is applied to the other gate of each transistor in parallel. The modulated output signal appears between the drains of the transistors.

Field-effect transistors with self registered gate which acts as diffusion mask during formation

Abstract: Self-registered field-effect transistors are built by forming the gate thereof at the same time the channel-adjacent portion of the source and drain regions are defined. In one embodiment a refractory metallic film is deposited over an insulating film and etched to form the gate. Subsequently, the metallic film may serve as a diffusion mask, although this is not essential. The metallic film is patterned by photoresist masking and etching. The portion of the metallic film overlying the channel region of the semiconductor body thereof is used as a gate. As a result of simultaneous definition of the channel-adjacent portions of source and draining regions and patterning of the channel-aligned portions of the gate, when source and drain regions are formed by diffusion of activators into the silicon wafer, automatic registration of the gate-adjacent portions of the source and drain junctions beneath the gate is achieved.

Resistance controlled timed pulse generator

Abstract: An electronic switching circuit responsive to a change of resistance in a sensing element, which circuit includes an insulated gate field effect transistor, a source of power, switching means interconnecting the source of power and the said transistor and a resistive sensing element interconnecting the gate of the said transistor and the power source, whereby the resistance of the sensing element controls the time required to charge the gate capacitance of the transistor and whereby the switching means opens the circuit delivering power to the transistor at such time as the gate capacitance is substantially charged.

Mos semiconductor device operable with a positive or negative voltage on the gate electrode and method therefor

Abstract: This disclosure relates to a field-effect transistor-type (MOS) device which is operable with either a positive or negative voltage applied to the gate electrode. In one state of operation, a potential of one amount applied to the gate serves to turn on the field-effect device (forms a channel) to conduct current from the source region to the drain region of the device. In another state of operation, a potential of opposite polarity applied to the same gate electrode serves to turn on the device by means of the tunneling of electrons through the gate insulator into the channel or substrate area located between the source and drain regions. This electron tunneling effect occurs due to the thinness of the insulator layer located between the gate electrode and the semiconductor substrate surface. This latter state of operation provides very fast FET action.

Room Temperature Instabilities Observed on Silicon Gate Devices

Abstract: A room temperature ionic instability has been observed on p-channel silicon gate MOS devices processed in a specific manner. This instability appears as a rapid and substantial change of threshold voltage at room temperature consistent with a fast moving ionic species in the gate oxide region. The diffusion constant of this species, measured over the temperature range from 0°C to 75°C is consistent with extrapolated data for H+ ions in SiO2. The magnitude of the room temperature threshold shift is voltage dependent and exists independently of any Na+ contamination. Correctly processed silicon gate devices are completely stable.

Reach through or punch{13 through breakdown for gate protection in mos devices

Abstract: The gate dielectric of an MOS device is protected from voltage surges by forming a PN-junction in parallel with the gate between the voltage source and ground, and directly above a region of highly conductive semiconductor material.

Method of making an insulated gate field effect device

Abstract: An insulated gate field effect device is made by a vapor etch and epitaxial refill technique The vapor etch into a first-type conductivity silicon substrate results in an undercutting between windows such that a cavity is developed completely beneath the insulator separating the window regions The cavity is then refilled epitaxially with silicon of a second conductivity type; a shallow layer of heavily doped silicon of said first-type conductivity epitaxially regrown in the window area; the gate insulator oxide thinned by etching; and gate, source, and drain contacts made

Method of making a junction type field effect transistor

Abstract: A METHOD OF MAKING A DIFFUSED JUNCTION TYPE FIELD EFFECT TRANSISTOR, WHEREIN AN ANNULAR P TYPE GATE REGION HAVING A PROTRUDING PORTION CONNECTED TO A P TYPE SILICON SUBSTRATE ACROSS AN N TYPE SOURCE REGION IS PRELIMINARILY FORMED, AND AFTER MEASURING THE ELECTRICAL CHARACTERISTICS BETWEEN THE SOURCE AND A DRAIN REGION, THE PROTRUDING PORTION IS HEAVILY DOPED WITH AN N TYPE DETERMINING IMPURITY SO AS TO ISOLATE THE ANNULAR P TYPE GATE REGION AND THE SUBSTRATE. D R A W I N G