Showing papers on "Gate oxide published in 1971"

Radiation Hardening of P-MOS Devices by Optimization of the Thermal Si02 Gate Insulator

Abstract: It has been found for p-channel MOS devices that considerably better radiation tolerance than generally believed possible can be obtained with gate insulators of thermally grown SiO2, provided that the processing conditions are optimized for radiation resistance. The oxidation ambient and temperature, the post-oxidation annealing temperature, the silicon orientation, and the method of depositing the gate metal all have pronounced effects on the radiation-induced degradation. With these parameters optimized for radiation hardness, gate threshold shifts of less than one volt after 1 × 106 rads (Si) can be obtained over the entire range of gate biases from 0 to -30 volts. This paper describes these findings and their applicability to the fabrication of radiation-hardened MOS circuits.

Memory Behavior in a Floating-Gate Avalanche-Injection MOS (famos) Structure

Abstract: A novel charge‐storage structure is described. The floating‐gate avalanche‐injection MOS (FAMOS) structure is shown to exhibit memory behavior in the form of long‐term charge storage on the floating conductive gate of an insulated gate field‐effect device. Charge is stored in the floating polysilicon gate by avalanche injection of electrons from an underlying p‐n junction.

D.C. measurement of the space charge capacitance and impurity profile beneath the gate of an MOST

Abstract: An analysis of the MOS Transistor with bias between the source and substrate has shown that when the surface is weakly inverted, the silicon space charge capacitance over a wide range of temperature and bias can be obtained from the change in gate voltage required to maintain a constant channel current. The substrate impurity profile beneath the gate oxide can then be calculated from capacitance-bias measurements. Measurements made on n -channell and p -channel transistors following the growth of a thick gate oxide indicate a segregation coefficient of ⋍ 0·3 and ⋍ 100 for boron and phosphorus respectively.

Modification of channel regions in insulated gate field effect transistors

Abstract: Method of producing channel regions in IGFET''s by implanting ions in the gate region through the gate, the gate of polycrystalline silicon material. The method both produces conducting channel regions and removes conducting channel regions. Enhancement mode and depletion mode transistors can be made. Other devices, such as resistors, can be formed simultaneously or sequentially by the implantation step.

Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor

Abstract: There is disclosed an improved junction field effect transistor with dielectric isolation as opposed to isolation by PN junction techniques. The use of the dielectric isolation lowers parasitic capacitance and permits the use of a single gate for the control of the current from the source to the drain of the device. The use of a single gate and the dielectric isolation prevents this parasitic capacitance and the concomitant reduction of the frequency response of the device by eliminating the need for a large area second gate which generates the unwanted parasitic capacitance. In the two gate embodiment of the subject invention, the second gate area is minimized so as to minimize the parasitic capacitance. The gain of the subject device is increased by internally connecting the two gates with a deep diffused region therebetween. There is further disclosed a method for making junction field effect transistors such that the channel width is accurately controlled.

Method of manufacturing an n-channel mos field-effect transistor

Abstract: The process for fabricating an N-channel enhancement type fieldeffect semiconductor device includes the step of implanting impurity atoms to form a channel region in a high resistivity substrate between the source and drain regions. By utilizing ion implantation, the amount and location of impurities can be accurately controlled. During the subsequent growth of the gate oxide layer, the impurity distribution is changed to provide a semiconductor device having the desired operating characteristics.

Over voltage protection circuit lateral bipolar transistor with gated collector junction

Abstract: An over voltage protection circuit, especially adapted for the protection of field effect transistor gate dielectric material and other circuit structures against high voltage, high peak current, short duration impulses such as produced by static electricity. The gate of the protected FET is shunted to ground by a lateral bipolar transistor whose collector junction is passivated by a layer of silicon dioxide thinner than the passivation layer at other locations. The silicon dioxide layer is covered by a metallization layer which extends from above the collector junction and makes contact to the emitter and to the substrate. The substrate contact is connected to a source of fixed potential. The collector is connected to the gate of the protected FET.

Floating gate solid state storage device and method for charging and discharging same

Abstract: A floating gate solid state storage device comprising a floating silicon or metal gate in a field effect device which is particularly useful in integrated circuit devices such as a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO2 is charged by transferring charged particles (i.e., electrons) at relatively low voltages (e.g., less than approximately 50 volts) across a thick insulation layer (e.g., greater than approximately 500 angstroms) from the substrate during an avalanche injection condition.

Solid state imaging device with fet sensor

Abstract: A solid state imaging device is described. Junction FETs are employed as the sensors in a charge storage mode. In the nonilluminated condition, each FET has its channel blocked by a depletion region formed by pulsing the gate. Under illumination, the depletion region withdraws, opening up the channel. Each imaging FET element is sensed by pulsing its source or drain, following which its gate is pulsed to reblock the channel. Also, an integrated circuit version of the device, the photo-JFETs having annular photo-gate regions and having a common substrate gate, the color response of the device being controlled by bias on the substrate gate.

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

Abstract: A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO 2 energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to 2 \times 10^{-4} A/cm2. The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.

Gate protection of MIS devices

Abstract: Gate shorts caused by electrical breakdown of the gate dielectric are a major yield and reliability problem for MOS transistors and integrated circuits. Diodes or diffused resistors with breakdown voltages of about 40 V can be used to protect the gate from high voltage transients or static discharges. This paper provides a uniform approach to gate protection. It is shown theoretically that in order to obtain effective gate protection: the protecting device should have a low dynamic resistance in breakdown; the breakdown voltage of the protecting device should be above, but close to, the maximum gate operating voltage; and protection by a diffused resistor in series with the gate is much more effective than by a diode in parallel with the gate. It is shown experimentally that, compared to the widely used fieldplate-induced breakdown, breakdown due to reach-through to a highly doped substrate provides: a dynamic resistance that is almost two orders of magnitude lower; reasonable control of the breakdown voltage; much better protection against simulated static discharges. Since under pilot line conditions no adverse effects on performance or yield have been observed, reach-through breakdown devices seem to improve gate protection decisively without any coincident disadvantages.

Planar silicon gate mos process

Abstract: THIS INVENTION REFERS TO A METHOD OF MANUFACTURING A METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAV- ING A SOURCE, DRAIN AN CHANNEL REGION AND A GATE FORMED OVER THE CHANNEL REGION. THERE IS FORMED A FIRST INSULATING LAYER ON A SEMICONDUCTOR SUBSTRATE COVERING THE NON-ACITVE REGIONS OF THE TRANSISTOR AND THEN A SECOND INSULATING LAYER IS FORMED OVER THE ACTIVE REGION OF THE TRANSISTOR. A SEMICONDUCTIVE LAYER IS DEPOSITED OVER THE ACTIVE AND NON-ACTIVE REGIONS AND SUBSEQUENTLY THE GATE PERIPHERY OF THE SEMICONDUCTOR LAYER IS CONVERTED TO AN OXIDE WHICH IS SUBSEQUENTLY ETCHED AWAY THUS EXPOSING THE SOURCE AND DRAIN REGIONS OF THE TRANSISTOR AND THE REAMINDER OF THE GATE PERIPHERY TO THE SUBSTRATE SURFACE. THE GATE AND SOURCE AND DRAIN REGIONS ARE THEN DIFFUSED WITH A DOPING IMPURITY AND METAL CONTACTS ARE DEPOSITED TO THE SOURCE AND DRAIN REGIONS AND TO THE GATE SEMICONDUCTOR.

Channel Shortening in MOS Transistors during Junction Walk‐Out

Abstract: The walk‐out of the breakdown voltage of the junctions of p‐channel MOS transistors was found to be accompanied by an increase in the transconductance. An explanation for this relationship is offered here in terms of electron injection into the gate oxide near the junctions, and subsequent trapping there. The rate of junction walk‐out depends not only on the total injected negative charge, but also on the value of the injection current itself, increasing at higher injection currents. The ratio of the injection current to the total junction current is found to decrease with increasing breakdown voltage.

Insulated gate field effect transistor circuits and their method of fabrication

Abstract: Insulated gate field effect transistor circuits utilizing transistors having a self-aligned gate, reduced parasitic capacitance and lower surface step-heights are fabricated with three levels of interconnects. The self-aligned gate transistors are fabricated with the use of a silicon nitride diffusion mask which also serves as an oxidation barrier in the formation of a thick oxide over the source and drain regions. Diffused interconnects are formed simultaneously with the source and drain region diffusions. The silicon nitride is then replaced with a more suitable dielectric, followed by the formation of polycrystalline silicon interconnects to provide source, drain and gate electrodes, and to provide a second level of interconnects which cross over the diffused interconnects at desired locations. An insulating layer is formed over the silicon interconnects and a metallization interconnect pattern, which crosses over the silicon interconnects at various desired locations is then formed to complete the circuit.

Insulated-gate field effect transistor having gate protection diode

Abstract: An insulated-gate field effect transistor is described which comprises a semiconductor substrate in which an insulated gate field effect transistor, and first and second regions having impurities at a high concentrations are formed. The first region is of the opposite conductivity type as that of the substrate, while the second region is of the same conductivity type as that of the substrate. The second region is in contact with one end of the first region, and the second region and/or the substrate is grounded. The end of the first region in contact with the second region is connected to the gate electrode of the insulated gate field effect transistor, and the other end of the first region is connected to the input electrode.

Enhancement mode n-channel mos structure and method

Abstract: Enhancement mode N-channel MOS structure having a semiconductor body with a region of P conductivity type formed in the body and extending to the surface. A polycrystalline gate structure is formed on said surface. Spaced source and drain regions are formed in the region of P conductivity type and form a channel in said body underlying said gate structure with the polycrystalline material of the gate structure having an N-type impurity therein. A layer of insulating material is formed on the surface and covers the gate structure. Contact elements are formed on the layer of insulating material and extend therethrough to make contact with the source and drain regions and said polycrystalline gate structure to form an active device. In the method for fabricating the structure, the polycrystalline material of the polycrystalline gate structure is doped independently of doping for forming the channel underlying the polycrystalline gate structure.

Production of silicon insulated gate and ion implanted field effect transistor

Abstract: THIS IS A METHOD OF MANUFACTURING A METAL INSULATOR SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A SOURCE, DRAIN AND CHANNEL REGION, AND A GATE FORMED OVER THE CHANNEL REGION. THE FIELD INSULATOR IS FIRST FORMED ON A SEMICONDUCTOR SUBSTRATE, WHICH SUBSTRATE IS OF ONE CONDUCTIVITY TYPE. A POLYCRYSTALLINE SILICON LAYER IS SELECTIVELY FORMED OVER THAT PORTION OF THE INSULATING LAYER WHICH OVERLIES THE CHANNEL REGION. FIRST AND SECOND OPENINGS ARE FORMED IN THE INSULATING LAYER ADJACENT TO THE GATE REGION. THE SEMICONDUCTOR BODY IS THEN SUBJECTED TO ION IMPLATATION OF THE DOPING IMPURITIES OF OPPOSITE CONDUCTIVITY TYPE THROUGH SAID OPENINGS TO FORM THE RESPECTIVE SOURCE AND DRAIN REGIONS. ELECTRICAL CONTACTS ARE THEN FORMED TO THE SOURCE, GATE AND DRAIN.

Method of making an mos transistor including a gate insulator layer of aluminum oxide and the article so produced

Abstract: A method of making an MOS transistor which has a gate insulator layer composed of aluminum oxide made by plasma anodizing a thin layer of aluminum, in which the thin aluminum layer and the anodized layer are not defined by etching. The gate electrode insulator layer is formed by depositing a thin layer of aluminum over the entire surface of the device after the source and drain contacts are made and then converting the entire aluminum layer to aluminum oxide.

Transistor comprising layers of silicon dioxide and silicon nitride

Abstract: A semiconductor structure in which a substrate having surface regions of opposite type conductivity is covered with two different insulating layers. In a specific structure, the regions in the substrate form an isolated gate field effect transistor with a thin layer of silicon nitride forming the insulation in the gate portion and a thicker layer of silicon dioxide forming the insulation over the remainder of the device.

Variable delay,mos,monostable pulse generating circuit

Abstract: There is disclosed a voltage controlled pulse width, MOS, monostable circuit which comprises first and second enhancement mode MOS transistors wherein the gate electrode of the second MOS transistor is connected to the drain electrode of the first MOS transistor and the gate electrode of the first MOS transistor is connected to an RC timing circuit of which the resistor is connected between the gate electrode and the source electrode and the capacitor is connected from the gate electrode to the drain electrode of the second MOS transistor. The MOS transistors are adapted to be connected across a source of power and a third enhancement mode MOS transistor is connected as a source follower between the drain of the second MOS transistor and the source of power. A fourth enhancement mode MOS transistor is connected across the first transistor and includes a differentiating circuit connected to its gate electrode for introducing a sharp pulse into the monostable circuit for initiating its operation. The terminal of the differentiating circuit and the gate electrode of the third transistor are adapted to be supplied with the gate pulse which initiates operation of the circuit to generate an output pulse and whose amplitude determines the width, or time duration, of the output pulse.

Radiation hardening of mos devices by boron

Abstract: A NOVEL TECHNIQUE IS DISCLOSED FOR RADIATION HARDENING OF MOS DEVICES AND SPECIFICALLY FOR STABILIZING THE GATE THRESHOLD POTENTIAL AT ROOM TEMPERATURE OF A RADIATION SUBJECTED MOS FIELD-EFFECT DEVICE OF THE TYPE HAVING A SEMICONDUCTOR SUBSTRATE, AN INSULATING LAYER OF OXIDE ON THE SUBSTRATE, AND A GATE ELECTRODE DISPOSED ON THE INSULATING LAYER. IN THE PREFERRED EMBODIMENT, THE NOVEL INVENTIVE TECHNIQUE CONTEMPLATES THE INTRODUCTION OF BORON INTO THE INSULATING OXIDE, THE BORON BEING INTRODUCED WITHIN A LAYER OF THE OXIDE OF ABOUT 100 A-300 A THICKNESS IMMEDIATELY ADJACENT THE SEMICONDUCTOR-INSULATOR INTERFACE, THE CONCENTRATION OF BORON IN THE OXIDE LAYER IS PREFERABLY MAINTAINED ON THE ORDER OF 10**18 ATOMS/CM.3. TH NOVEL TECHNIQUE SERVES TO REDUCE AND SUBSTANTIALLY ANNIHILATE RADIATION INDUCED POSITIVE GATE CHARGE ACCUMULATIONS, WHICH ACCUMULATIONS, IF NOT ELIMINATED, WOULD CAUSE SHIFTING OF THE GATE THRESHOLD POTENTIAL OF A RADIATION SUBJECTED MOS DEVICE, AND THUS RENDER THE DEVICE UNSTABLE AND/OR INOPERATIVE.

Gate oxide early fail screening test utilizing a low pressure plasma

Abstract: A method of accelerating early gate oxide failures in Field Effect transistor devices. This method uses a d.c. glow discharge or plasma as a means for electrically inducing, on the gate electrode of such Field Effect Transistors, an electrical potential sufficient to stress the gate oxide under the electrode to a level higher than that seen in normal service. This stressing of the gate oxide is sufficient to cause in a short period of time the failure of those gate oxides which would normally fail within the first few hundred hours of use in the field. The described method accomplishes this very desirable result without affecting those other gate oxides which will perform satisfactorily in service. This use of a plasma or glow discharge to induce the stressing voltage of the gate oxide eliminates the need of mechanically contacting each and every unit. The method of the invention, therefore, not only permits the batch stressing of such units during the production cycle, while the units are still incorporated in a wafer, but further allows subsequent testing of the units whether they be individual FET devices or whether they be corporated in an integrated circuit design.

A high voltage ion-implanted MOSFET

Abstract: The drain breakdown voltage of usual p-channel MOS devices is limited to about 30 to 40 V by field crowding at the drain junction. By optimizing certain design parameters like diffusion depth, substrate resistivity and gate oxide thickness, 80 V breakdowns can be achieved. To date, higher breakdowns are only possible with special device geometries (e.g. the stacked gate tetrode) which are generally not compatible with common MOS processes. By adding an ion-implantation step to the conventional aluminum-gate MOS process, it is possible to fabricate MOSSFET's with source-drain breakdown potentials of greater than 240 V on the same chip with conventional MOS circuitry. The device looks identical to the conventional MOSFET except that an unmetalized gate oxide region is left between the gate and the drain juction. During a subsequent ion-implantation this portion of the channel is lightly doped with a p-type dopant in the case of p-channel devices. Since-both the metal and the field oxide are thick enough to stop all ions, the implantation affects only the high voltage devices on the wafer. The implanted channel has the effect of reducing the field in the vicinity of the drain junction, thereby increasing the source-drain breakdown voltage. P-channel devices were made on 10 Ω-cm material using 1µm diffused junctions. The aluminum gate was 10 µm long and the implanted channel was 25µm long. Breakdowns up to 240 V were achieved after an optimum dose of 2 \times 10^{12} boron ions/cm2were implanted at 80 keV through 1300 A of gate SiO 2 . The wafers were subsequently annealed for 15 minutes at 525°C in N 2 . Implanted resistors made at the same time had sheet resistivities of 25 kΩ/□. Of critical importance in obtaining best results are low threshold voltages and accurate implantation dose control To obtain long term reliability it is necessary to prevent charge build-up on the oxide over the implanted channel. This is accomplished by the deposition of a layer of phosphosilicate glass after ion-implantation. It is now possible to include decoding circuitry on the same chip as the high voltage drivers for display tubes.

Silicon gate fet-niobium oxide diode-memory cell

Abstract: A high density memory cell comprising a silicon gate field effect transistor and a bismuth-niobium oxide-niobium bistable switching diode integrally formed over the drain electrode of the FET. The memory cell is formed by providing an oxidized P silicon wafer, stripping the oxide from the source, drain and gate region of the FET and regrowing the gate oxide. Polycrystalline silicon is deposited on the regrown gate oxide and the polysilicon is subtractively etched to delineate the gate electrode. Source and drain openings are etched using the remaining polysilicon as part of the etchant mask. An N+ diffusion is made to form the source and drain region and to dope the polycrystalline silicon FET gate electrode. The device is reoxidized and contact holes are opened to the source and drain region. Platinum-silicon is used to form the source and drain ohmic contacts. Niobium is deposited and subtractively etched except over the drain contact. Niobium oxide is formed by a wet anodizing step. Bismuth is deposited and subtractively etched except on the niobium oxide. Aluminum is deposited and subtractively etched to provide conducting pathways for contacting the source and the bismuth electrodes of the memory cell.

Semiconductor device with two mos transistors of non-symmetrical type

Abstract: A semiconductor device constituted by two MOS transistors of diffusion-self-alignment type, the source electrode and the gate electrode of one transistor being connected with the source electrode and the gate electrode of the other transistor, respectively. In the device, the mutually connected gate electrodes serve as a new gate electrode, while the drain electrode of said one transistor serves as a new drain electrode and the drain electrode of said other transistor serves as a new source electrode.

Methods of producing field effect transistors having insulated control electrodes

Abstract: A method of producing a field effect transistor having an insulated gate electrode in which at least one surface of a semiconductor body is covered with an insulating layer, a region of the insulating layer is covered with a metal layer to form the gate electrode and contact-making windows are introduced into the insulating layer to make contact with a source and drain electrode provided in the semi-conductor body.

Techniques for minimizing MOSFET gate leakage current

Abstract: Measurements made on the gate current of one side of a dual MOSFET show that special packaging and circuit techniques result in a substantial reduction in gate leakage by almost entirely eliminating header leakages. Gate currents as low as 20×10-18A have been measured during the investigation. Details of the measuring techniques are also given.

The channel-conductance increase of conventional MOS transistors by avalanche injection: Application to read-only memory

Abstract: The walk-out phenomena of the avalanche breakdown voltage at the drain junction of MOS transistors is caused by injection of hot carriers from the avalanche plasma into the gate oxide. This paper reports detailed data of this phenomenon observed in conventional Al or Si gate, p- and n-channel transistors of a narrow channel, L = 1.5 \sim 2\micro m, aiming at a low-cost, electrically programmable ROM. The p-channel transistor, for example, of 5Ω-cm, n-Si, t ox = 3000A, L = 2µm, W = 50µm, Vth = -4V, can be changed to a completely normally "on" transistor (Vth = 6V), after applying a -96V through a 10kΩ resistor, for 1.5 sec, to the source and drain junctions, the gate electrode being connected to the substrate. The estimated electron density trapped near the Si-SiO 2 interface is \sim 7 \times 10^{11} /cm2, and the capture probability defined as the ratio of the trapped charges to the integrated avalanche current is 5 \times 10^{-11} . When the gate is biased to +50V in order to accelerate the carrier injection, the necessary pulse duration is down to 120 msec. This can be further lowered by design optimization. For the n-channel transistors the hole injection is about three orders of magnitude lower than the electron injection in the p-channel case, because of higher barrier height for holes (3.8eV) than forelectrons (3.15 eV).

Effects of Ionizing Radiation on Thin-Film Semiconductor Devices

Abstract: Results of an investigation of the transient and permanent effects of ionizing radiation on Al2O3-CdSe thin-film transistors and microcircuits are reported. The total-gamma-dose response of the devices did not differ significantly from that of conventional silicon MOS devices, and the observed shift in threshold voltage is consistent with a positive charge buildup in the gate oxide. In transient response studies, it was found that the thin-film devices will perform without failure up to peak dose rates of ~1010 rads(Si)/s (~30 ns pulsewidth).