Showing papers on "Gate oxide published in 1972"

Fundamental limitations in microelectronics—I. MOS technology

Abstract: The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2.

Low level currents in insulated gate field effect transistors

Abstract: A theory for low-level current operation in Insulated Gate Field Effect Transistors is developed. Using the depletion approximation for the semiconductor surface potential, an analytical expression is obtained which is accurate for gate voltages corresponding to surface operation from depletion to the onset of strong inversion. Numerical calculations that avoid the limitations on gate voltage have shown the theory to hold as well for surface potentials corresponding to strong inversion.

Threshold shift calculations for ion implanted MOS devices

Abstract: The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO 2 interface. These shallow implants ( μ m) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO 2 is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.

Method for stabilizing fet devices having silicon gates and composite nitride-oxide gate dielectrics

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode. Annealing at 1,050 DEG C applied for a duration of one-half to one hour produces excellent results.

Method of making a semi planar insulated gate field-effect transistor device with implanted field

Abstract: A semi-planar insulated gate field effect transistor integrated circuit device having an ion implanted field region to achieve high field inversion voltage. The field effect transistor is fabricated on an elevated region of P-type silicon surrounded by and aligned to an implanted P-type field region. A thick field oxide layer on the implanted P-type field region surrounds and extends somewhat above the elevated region of P-type silicon in which the field effect transistor is fabricated. The field effect transistor includes N+ source and drain regions, a gate oxide insulator, a gate electrode and an interconnect metal layer provided in the elevated active region of P-type silicon. The method of manufacturing includes thermally growing a high integrity oxide layer on the P-type substrate, depositing a layer of nitride thereon, and removing the nitride over the field region, thereby leaving nitride over the active region of the silicon. The surface of the device is bombarded with boron ions to produce an implanted layer in the field region, with the nitride serving as an implant mask. The boron ions are then redistributed by application of a heat cycle. A thermal oxidation step increases the thickness of the oxide over the field, causing a deeper implanted P-type field region to be formed. The surface concentration of the implanted field region is increased by a subsequent heat cycle to compensate for boron ions depleted at the oxide-silicon interface during the oxidation cycle. The oxide formed on the nitride is removed and the field effect transistor is provided in the active region in a conventional manner.

Vertical channel junction field-effect transistors and method of manufacture

Abstract: The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

Low voltage charge storage memory element

Abstract: A variable threshold, dual insulator, insulated gate field effect transistor charge storage memory element comprises a relatively thin barrier layer of silicon dioxide adjacent to the semiconductor surface which has disposed thereon, beneath the gate metalization, a somewhat thicker layer of an insulator having a dielectric constant over 18. Dielectric materials include: strontium titanate (SrTiO3), titanium dioxide (TiO2), lead zirconate (PbZrO3); refractory metal oxides, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), tantalum oxide (Ta2O5), and tungsten oxide (WO3); rare earth metal oxides; and ferroelectrics and antiferroelectrics.

Subthreshold drain leakage currents in MOS field-effect transistors

Abstract: There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (V tx ) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage V i , the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between V i and V tx the surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below V tx . The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.

Field effect semiconductor device having an unsaturated triode vacuum tube characteristi

Abstract: A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain volage is above the threshold voltage exhibiting a linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.

Insulated-gate field effect semiconductor device having low and stable gate threshold voltage

Abstract: An insulated-gate field effect transistor includes a gate electrode composed of a tantalum layer and an aluminum layer. An insulating film composed of a tantalum oxide layer and an aluminum oxide layer is disposed about the gate electrode and insulates the gate electrode from the source and drain electrodes. In the fabrication of the device, the aluminum oxide and tantalum oxide layers are formed by anodic oxidation.

Method of making insulated gate field effect transistor

Abstract: The present invention relates to an insulated gate field effect transistor and method of making same. An aluminum film is evaporated on a silicon wafer. Portions of the aluminum film are masked. The unmasked portions are anodized. The unanodized portions are removed leaving the anodized insulative portions thereon. Dopant atoms are diffused into areas of the silicon wafer which are not covered by the anodized insulative layer. The anodized insulative layer acts as a diffusion mask, to form source and drain regions in the silicon wafer, and to thus delineate a gate insulator layer between the source and drain regions by the act of diffusion. A second aluminum film is evaporated over the silicon wafer. The portions of the areas of the second aluminum film over the source and drain regions, and the area of the second aluminum film over the aligned gate insulator layer are masked. The unmasked portions of the second aluminum film are anodized to delineate an aligned gate electrode over the aligned gate insulator layer and to delineate source and drain electrodes in contact with the source and drain regions. An insulated gate field effect transistor is thus formed.

A semi-insulated gate gallium-arsenide field-effect transistor

Abstract: Proton bombardment has been used to make a semi-insulated gate gallium-arsenide field-effect transistor. This technique combines the simplicity of the metal semiconductor FET technique, the advantage of operating the device using positive as well as negative bias on the gate, and the possible use of higher conductivity material for the channel, which may result in a higher transconductance and a higher saturated current density.

Shielded silicon gate complementary MOS integrated circuit

Abstract: An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.

Complementary field effect transistors having p doped silicon gates

Abstract: AN INSULATING GATE COMPLEMENTARY FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT USES SILICON AS THE GATE ELECTRODE. THE GATES OF BOTH N- AND P- CHANNEL TRANSISTORS ARE DOPED WITH P TYPE IMPURITIES, THEREBY BALANCING THE VOLTAGE THRESHOLD CHARACTERISTICS OF THE TRANSISTORS. THE GATE INSULATOR IS DUAL NITRIDE-OXIDE TYPE, WHICH, IN COMBINATION WITH THE P-TYPE GATES, RESULTS IN A HIGH SURFACE-STATE CHARGE DENSITY, AND REQUIRES PARTICULAR DOPING VALUES FOR THE CHANNELS OF THE COMPLEMENTARY TRANSISTORS.

Method of producing a silicon gate insulated-gate field effect transistor

Abstract: A method is disclosed for fabricating an insulated gate field effect transistor having a silicon gate electrode. The silicon gate electrode is covered with a first insulating layer. That layer as well as the surfaces of the source and drain regions are thereafter covered with a second insulating layer. The second insulating layer is selectively removed to expose a portion of the first insulating layer covering the silicon gate electrode and a part of the surfaces of the source and drain regions. Source and drain electrodes are then respectively applied to the source and drain regions without the possibility of a drain-togate or source-to-gate short circuit.

Method of forming silicon gate device structures with two or more gate levels

Abstract: Semiconductor device structures having multiple gate levels. The gate levels are composed of polycrystalline silicon. A single device may have two or more gate levels, separated by a dielectric, or different devices of a common structure may have differing threshold voltages by specific selection of particular polycrystalline silicon layers.

Field effect transistor having back-to-back diodes connected to the gate electrode and having a protective layer between the source and the diodes to prevent thyristor action

Abstract: An insulated gate field effect transistor having protective means for the gate insulator layer. The protection means comprises two back-to-back diodes connected to the gate electrode. The source region of the FET is partially encompassed by a relatively high impurity concentration region of opposite conductivity type to that of the source region. The encompassing region of relatively high impurity concentration is of the same impurity as that of the substrate and is so located that there is no thyristor action between the source and the diodes.

Method of fabrication of insulated gate field effect semiconductor devices

Abstract: An insulated gate field effect transistor having a self-aligned gate, reduced capacitance, and lower surface step heights is fabricated with the use of a silicon nitride layer which serves first as a diffusion mask, than as an oxidation barrier, and ultimately as a gate dielectric. In an alternate embodiment, lower threshold voltages are achieved by replacing the initial gate dielectric with a thinner dielectric having a reduced surface state density.

Non-volatile semiconductor storage device utilizing avalanche injection and extraction of stored information

Abstract: A non-volatile semiconductor storage device that can be electronically erased can be realized from a double gate field effect transistor having a first and second gates, the first gate being closer to the semiconductor body than the second gate and insulated from the body and the second gate so that it is electrically floating. When the floating gate has a thickness and is biased so that complete depletion can be achieved therein and the thickness and ionization rate product is equal to unity stored information in the form of electrons are expelled therefrom due to the effects of avalanche mechanisms.

Insulated dual gate field-effect transistor signal translator having means for reducing its sensitivity to supply voltage variations

Abstract: An oscillator circuit is described using a dual gate MOS-FET transistor. Drift of the oscillating frequency of the oscillator circuit caused by drain supply voltage variations is minimized by suitable bias voltages applied to the two gates. The gate bias voltages are derived from the same principle supply, but the gate voltage variations must be nonlinear with respect to the drain voltage variations to achieve frequency stability. The suitable gate voltages are achieved by means of a voltage divider composed of dual gate MOS-FET transistors.

Mos semiconductor structure with increased field threshold and method for making the same

Abstract: An MOS semiconductor structure and method for making the same in which a semiconductor wafer is treated to form an thin oxide layer having a net charge. In a specific embodiment a positive net charge is introduced into the oxide layer through introduction of chrome ions. Field oxide is then grown over the thin oxide layer. The field oxide and thin oxide layers are removed from selective portions of the semiconductor wafer. Source and drain diffusions are made into the semiconductor wafer and a gate oxide along with gate source and drain electrodes are formed. The introduction of the positive oxide charge over the field region increases the field voltage threshold and permits use of a thinner field oxide.

Semiconductor device and the method of making the same

Abstract: A semiconductor device comprising a p type semiconductor substrate including an n channel depletion mode metal-oxide-semiconductor field effect transistor provided with a gate insulating double layer formed of a silicon oxide layer and a phosphosilicate glass layer and an n channel enhancement mode metal-oxide-semiconductor field effect transistor provided with a gate insulating double layer formed of a silicon oxide layer and an alumina layer, the portions of the semiconductor substrate other than those where the field effect transistors are formed being provided with a double layer of a silicon oxide layer and an alumina layer, or of an alumina layer and a phosphosilicate glass layer.

Resistive gate field effect transistor

Abstract: A resistive gate field effect transistor (FET) is disclosed in which the gate comprises a resistive film overlying an insulating layer and in contact with both the source and drain electrodes. This provides an integrated circuit, bidirectional voltage limiter in which the limiting voltage can be tailored to almost any value likely to be found on an integrated circuit. In another form of the present invention, a conductive gate is added between the resistive gate and the substrate.

Process for the formation of selfaligned silicon and aluminum gates

Abstract: A PROCESS FOR THE SIMULTANEOUS FORMATION OF SELFALIGNED SILICON GATES AND ALUMINUM GATES HAVING SELFALIGNED CHANNEL REGIONS ON THE SAME WAFER IS DISCLOSED. BASICALLY, THE PROCESS CONSISTS OF THE DEPOSITION OF SUCCESSIVE LAYERS OF SILICON NITRIDE AND POLYCRYSTALLINE SILICON OVER THICK AND THIN SILICON DIOXIDE REGIONS WHICH ARE DISPOSED ON THE SURFACE OF A SEMICONDUCTOR WAFER. POLYSILICON GATES ARE DELINEATED IN THE THIN OXIDE REGIONS. SUBSEQUENTLY, A CHEMICALLY VAPOR DEPOSITED SILICON DIOXIDE LAYER IS FORMED OVER THE SURFACE OF THE EXPOSED SILICON NITRIDE LAYER AND OVER THE POLYCRYSTALLINE SILICON GATE GEGIONS. AT THIS POINT, THE CVD OXIDE IS DELINEATED TO FORM AN OXIDE MASK WHICH WILL PERMIT THE REMOVAL OF SILICON NITRIDE DOWN TO THE THIN OXIDE AT CERTAIN REGIONS WHERE DIFFUSION WINDOWS ARE TO BE FORMED IN EXPOSED THIN OXIDE REGIONS WHICH ARE SUBSEQUENTLY REMOVED BY A DIP ETCH. WHILE THE EXPOSED THIN OXIDE REGIONS ARE MASKED BY EITHER SILICON NITRIDE PORTIONS OR POLYCRYSTALLINE SILICON GATE REGIONS, THE MASKING REGIONS OF CVD OXIDE WHICH PROTECTED THE SILICON NITRIDE LAYER ARE SIMULTANEOUSLY REMOVED BY THE DIP ETCH WHICH OPENS THE DIFFUSION WINDOWS IN THE THIN OXIDE REGIONS. AFTER A DIFFUSION STEP WHICH INCLUDES DEPOSITION OF A PHOSPHORUS DOPANT IN THE DIFFUSION WINDOWS FROM THE VAPOROUS PHASE AND A DRIVE-IN STEP, A THERMAL OXIDATION STEP IS CARRIED OUT WHICH COVERS THE DIFFUSED WINDOW REGIONS AND THE POLYSILICON GATES AND THICK OXIDE REGIONS LEAVING THE EXPOSED NITRIDE PORTIONS UNAFFECTED. IN A SUBSEQUENT MASKING STEP, DIFFUSION CONTACT WINDOWS AND SILICON GATES CONTACT WINDOWS ARE OPENED. THEN, METALLIZATION IS DEPOSITED EVERYWHERE AND DELINEATED TO FORM METAL GATES AND CONTACTS TO BOTH DIFFUSIONS AND SILICON GATES. METAL IS DELINEATED AND FORMED IN EACH OF THE EXPOSED SILICON NITRIDE REGIONS ONE OF WHICH IS A SELF-ALIGNED CHANNEL REGION FOR A METAL GATE FIELD-EFFECT TRANSISTOR. OTHER METAL GATES FOR A CHARGE COUPLED DEVICE ARE POSITIONED BY VIRTUE OF THE PRESENCE OF ADJACENT POLYSILICON GATES AND ARE INSULATED FROM THE SUBSTRATE BY A THIN OXIDE AND NITRIDE LAYER AND FROM THE SILICON GATES BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE ON THE SURFACE OF THE SILICON GATES. THE RESULTING STRUCTURE INCLUDES A METAL GATE FIELD-EFFECT TRANSISTOR, A SELF-ALIGNED SILICON GATE FIELD-EFFECT TRANSISTOR, AND A CHARGE COUPLED DEVICE ON THE SAME WAFER. BY USING AN ADDITIONAL MASKING STEP OVER THAT REQUIRED FOR THE FORMATION OF SILICON SELF-ALIGNED GATES ALONE, METAL GATES WHICH ARE EITHER SELF-ALIGNED BY VIRTUE OF ADJACENT POLYSILICON GATES OR BY VIRTUE OF THE PRESENCE OF A SELF-ALIGNED CHANNEL ARE THUS OBTAINED. IN ADDITION, A RANDOM ACCESS CHARGE COUPLED DEVICE WHICH INCORPORATES A METAL TRANSFER GATE AND A POLYSILICON STORAGE PLATE IS ALSO DISCLOSED. THE STRUCTURE RESULTS FROM THE ABOVE DESCRIBED FABRICATION PROCESS AND IS STRUCTURALLY UNIQUE IN THAT THE METAL GATE IS DISPOSED IMMEDIATELY ADJACENT TO A DIFFUSION REGION WHICH ITSELF IS DISPOSED UNDER A THICK OXIDE LAYER. IN ADDITION, THE POLYCRYSTALLINE SILICON STORAGE PLATE IS SPACED FROM THE METAL GATE BY A LAYER OF THERMALLY GROWN SILICON DIOXIDE.

Method and control circuit for liquid level control systems

Abstract: A control circuit having a gate with a liquid level detecting probe in the gate circuit of the gate. The probe controlled gate circuit has a resistor in series with a unidirectional device, which unidirectional device prevents the flow of stray line capacitance induced current from the probe connecting lines to the gate circuit. However the detection of liquid levels by the probe pulls sufficient current through the probe circuit, diode and resistor to close the gate.

Tetrode mosfet with gate safety diode within island zone

Abstract: A field-effect transistor having at least two insulated-gate electrodes comprises an island zone of the same conductivity type as the electrode zones (source and drain zones) situated between two gate electrodes. According to the invention an aperture is provided in said island zone in which aperture a circuit element is provided, particularly a safety diode, which is connected to a gate electrode. In this case a particularly simple and short connection is possible between the circuit element and a gate electrode.

Rf power transistor secondary breakdown protection circuit

Abstract: A protection circuit for RF power transistors to prevent secondary breakdown includes gate means to monitor both the collector current and collector voltage. A gate pulse generated each time the collector voltage exceeds a preset value is used to gate a wave form derived from the transistor collector current. When the current wave form is in phase with the gate pulse and is of sufficient amplitude, the gate means provides a controlled voltage to bias off the transistor power supply for purposes of reducing the output power to safe operating levels.

High-speed alterable, nonvolatile MIS memory

Abstract: A new type of Floating Si-Gate Tunnel Injection MIS (FTMIS) memory devide that switches within the nanosecond range was fabricated. The write/erase time of this device is found to be almost two orders of magnitude shorter than MAOS or MNOS devices. This device consists of a silicon substrate, oxide (20-40 A), highly resistive polycrystalline silicon film (200-1000 A) as a floating gate, gate oxide (800-1500A), and gate electrode. Most conventional tunnel injection memory devices utilize traps distributed near the insulator-insulator interface as the site of charge storage. This limits the switching speed. In our structure, the floating gate overcomes this weak point and the transition time constant depends only on the thin tunnelable oxide thickness. The FTMIS device features high-speed write and erase ( \lsim 50V ) and semipermanent retention (similar to MNOS). The gate oxide is formed by thermal oxidation of the upper part of the floating gate in an island structure. Thus leakage through pinholes has little influence on memory retention.

Control circuit for insulated gate field effect transistors

Abstract: The gate voltage of an insulated gate switching transistor is controlled by means of a pair of reverse biased Schottky barrier diodes connected in mutual series aiding electrical relationship. A common node or terminal between these diodes is connected to the gate of the transistor and to an electrical switch, in order to provide means for varying the total electrical impedance across one or the other of the diodes, and thereby to turn the transistor between the "ON" and "OFF" states thereof.