Showing papers on "Gate oxide published in 1973"

Nonavalanche injection of hot carriers into SiO2

Abstract: Carriers can be injected into the SiO2 from a junction reverse biased below avalanche and lying in the silicon near the Si–SiO2 interface. This effect was studied for electron injection in n‐channel MOS transistors. The electrons originated from a forward‐biased (supply) junction lying below the source, drain, and channel region. The electrons were heated in the space‐charge layers of source and drain reverse biased below avalanche breakdown and in the space‐charge layer below the channel induced by the combined effect of a positive gate voltage and the reverse bias on source and drain. Injection into the oxide occurs mainly from the latter region. The current through the oxide and the charge trapped in the oxide were measured as a function of several parameters. These measurements yield the threshold values of the reverse source (drain) voltage, VTR, and of the gate voltage, VGT, necessary for injection. From the dependence of VTR on the concentration of dopant in the channel region, the value of the mea...

Low capacitance V groove MOS NOR gate and method of manufacture

Abstract: An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

Process for fabricating MNOS non-volatile memories

Abstract: The switching speed of an MNOS field effect transistor is increased by a heat treatment in an ammonia rich atmosphere during processing. The transistor has an insulated gate structure comprising a layer of silicon nitride deposited on a layer of silicon oxide. After the formation of the silicon oxide layer and immediately prior to the formation of the silicon nitride layer on a surface thereof, the surface of the silicon oxide layer is heat treated in an ammonia enriched atmosphere to remove substantially all remaining oxygen atoms and molecules absorbed on the surface.

Method for forming MOS structure using double diffusion

Abstract: Method for forming a semiconductor structure by providing a semiconductor body having an impurity of one conductivity type and forming a gate oxide layer of relatively precise thickness which is not thereafter removed on the surface of the semiconductor body. A protective layer is then formed on the gate oxide to protect it from being etched and also from contamination. An opening is provided which exposes the surface of the semiconductor body adjacent the gate oxide. First and second impurities of opposite conductivity types are caused to enter through the opening utilizing one edge of the gate oxide as a mask to provide first and second regions within the semiconductor body of opposite conductivity types to form a precisely controlled channel. Source, gate and drain metallization is provided to complete the device.

Electrically alterable floating gate device and method for altering same

Abstract: A field effect device having a floating gate which can be charged or discharged electrically is disclosed. A pair of spaced apart regions in a substrate define a channel above which a floating gate is disposed and insulated from the channel. The regions have a conductivity type opposite to the substrate. A second gate is disposed above and insulated from the floating gate. The floating gate may be charged electrically by producing an avalanche breakdown at the junction formed by one of the spaced apart regions and the substrate causing the passage of electrons through the insulation onto the floating gate. The floating gate may be discharged by the application of a voltage to the second gate relative to the spaced apart regions and substrate causing the passage of electrons from the floating gate through the insulation onto the second gate.

Logic circuit arrangement employing insulated gate field effect transistors

Abstract: A logic circuit arrangement consisting of insulated gate field effect transistors of opposite channel types wherein the drain electrode of a single first insulated gate field effect transistor of one channel type is connected to the drain electrode of at least one second insulated gate field effect transistor of the opposite channel type constituting a logic gate. The gate electrode of second transistor is supplied with a data signal and the gate electrode of first transistor and the source electrode of second transistor are supplied with clock pulse signals bearing a complementary relationship with each other. The source electrode of first transistor may receive a clock pulse signal supplied to the source electrode of second transistor or constant voltage; and an output signal from the logic circuit is delivered from the junction of the first and second transistors.

Method for manufacturing ion implanted insulated gate field effect semiconductor transistor devices

Abstract: A method for manufacturing insulated gate field effect transistor devices utilizing ion implantation for elimination and suppression of mobile ion contamination is described and comprises bombarding and implanting hydrogen or helium into the dielectric insulating layer of an insulated gate field effect transistor at relatively low ion energy, followed by a comparatively low temperature anneal.

Method for making FET circuits

Abstract: An integrated circuit and process for manufacturing same is disclosed. The integrated circuit comprises both depletion and enhancement mode field effect transistors, each having silicon gates and self-aligned gate regions. The process includes forming a thick oxide layer on the substrate, removing the thick oxide at the transistor sites, forming a thin oxide at the transistor sites, masking selected transistor sites to selectively implant ions at the other sites, depositing a polysilicon layer over the slice and patterning the polysilicon layer to form gate electrodes, removing the thin oxide using the polysilicon gate electrodes as masks, diffusing the source and drain regions, forming an insulating oxide, then applying the source drain and gate contacts and interconnects.

Field effect semiconductor memory apparatus with a floating gate

Abstract: A field effect semiconductor memory apparatus with a floating gate which is so constructed that when a gate electrode is impressed with voltage, there is created across the floating gate and substrate an electric field stronger than, or at least as strong as, that prevailing across the floating gate and gate electrode, whereby the floating gate is stored with information by being impressed with a relatively low level of voltage and the stored information is extinguished by giving rise to an avalanche breakdown across the substrate and at least either of the source and drain.

Electrically erasable floating gate fet memory cell

Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

Method of forming self-aligned field effect transistor and charge-coupled device

Abstract: A semiconductor device containing in a single semiconductor body a self-aligned Field Effect Transistor and a Charge-Coupled Array having an improved capacity for storing charges. The device is formed by depositing both polysilicon and silicon nitride layers over a silicon dioxide layer on the surface of a silicon body and selectively etching these layers so that suitable dopants may be diffused or ion-implanted into selected areas of the underlying silicon body to form, in the same semiconductor body, an improved charge-coupled array having an improved self-aligned Field Effect Transistor associated therewith. This process not only results in a device in which the chance of an inversion layer under the oxide on the surface of the device is substantially reduced, but also provides a self-aligned Field Effect Transistor having a thinner gate oxide and a charge-coupled array that has an increased capacity for storing charges. The improved array so formed also has, during operation, zero spaced depletion regions so that unwanted electrical discontinuities between or within the depletion regions of the charge-coupled array are avoided. Because zero spacing is achieved by using these thin conducting layers, the metal phase lines can be made narrow thus leaving openings in the charge transfer channel making the device particularly suitable for imaging applications.

Method of making isolated complementary monolithic insulated gate field effect transistors

Abstract: Complementary insulated gate field effect transistors are formed in a thin semiconductor layer of a first conductivity type by first forming a dielectric layer on a surface of the semiconductor layer. A polycrystalline support is then formed on the dielectric layer. A lightly doped tub region of a second conductivity type is formed in the semiconductor layer extending to the dielectric layer. The lightly doped tub region is preferably formed by carrying out a conventional diffusion operation, then removing a portion of the thickness of the semiconductor layer which contains the highest dopant concentration. Regions serving as source and drain electrodes of a first and second field effect transistor are then formed in the lightly doped tub region and in the semiconductor layer. Gate electrodes are provided over an insulating layer on the surface of the semiconductor layer to complete fabrication of the complementary devices. The gate electrodes may be formed after the source and drain electrodes, or before them, in a self aligned embodiment.

Erasable floating gate device

Abstract: A metal-oxide-semiconductor (MOS) floating gate storage device is disclosed which includes a pair of spaced-apart regions (source and drain) disposed in a substrate below a floating gate which is completely surrounded by silicon oxide. The gate extends laterally to a third diffused region in the substrate. The floating gate which provides non-volatile storage for an electric charge is charged through avalanche injection and electrically discharged through the third region.

Solid state components

Abstract: There is disclosed a method of making a metal-oxide silicon field-effect transistor (MOSFET) capable of delivering substantial power (5 to 10 watts) in the microwave frequency range (about 5 Gigahertz) and operating as an amplifier over a wide bandwidth through a reasonably high input impedance exceeding about 5 ohms. The method is practiced with a layered blank of silicon having, say, an N+ substrate on which is a Player; there is a second N+ layer on the P-layer. Regions, each having a surface for deposit of a drain, are prepared on the second layer. Grooves are etched undercutting these regions so that they overhang the grooves. The gate and drain electrodes are deposited simultaneously by linear beams of vapor at supplementary angles to the prepared surfaces. The angles and the length of the overhangs are such that the gate electrodes extend only along the projections of the edges of the contiguous Players which extend along the groove, minimizing the capacitance between the gate electrode and the other electrodes. There is also disclosed a MOSFET produced in the practice of this invention.

Method of making a planar graded channel MOS transistor

Abstract: The method of fabrication of a planar narrow channel metal oxide semiconductor field effect transistor (MOSFET) by a double diffusion through a self-aligned silicon gate wherein a first type dopant is diffused into the same self-aligned window of the source diffusion already diffused with a second type dopant. The diffused source and drains are self-aligned by means of the silicon gate, thus permitting narrow gate lengths. The diffusion profile is such that the impurity concentration near the source is higher than that near the drain. When a reverse bias is applied between, for example, an n-type drain and a p-type diffused region, the depletion layer cannot widen as much toward the source as a uniform channel because of the impurity concentration profile. Thus a narrow channel length can be used withoout drain-source punch-through at low voltages. Meanwhile, the self-aligned silicon gate permits a close spacing between the source and drain contacts, thus reducing the feedback capacitance between the drain and the gate.

Radiation hardened mis devices

Abstract: An insulated gate field effect transistor is characterized by heavily doped source and drain regions separated by a channel in the surface layer of a silicon body. Above the silicon surface of the channel lies a metal layer constituting a gate electrode. The gate electrode is separated from a passivating layer immediately overlying the channel surface, by an open space having a width much greater than the thickness of the passivating layer. The open space is defined by the thickness of a layer of material formerly interposed between the metal layer and the passivating layer but subsequently removed during the fabrication of the field transistor.

Reversible floating‐gate memory

Abstract: Reversible memory behavior is reported for an insulated gate structure, in which charge is stored on a polysilicon gate. This gate is floating between layers of silicon dioxide (SiO2) and silicon nitride (Si3N4). The floating gate is charged negatively by hot carrier injection through the SiO2, from an avalanche plasma in the underlying silicon. This charge can then be removed by applying a positive voltage between an external gate and the silicon substrate. The positive voltage causes electrons to flow through the nitride layer. Both charge states are remembered when external bias voltages are removed. The importance of circuit configuration during charging is discussed, and improvements of injection efficiency for a favorable configuration are described.

Method of simultaneously making a sigfet and a mosfet

Abstract: A method comprising providing a gate electrode layer of polycrystalline silicon for a SIGFET, depositing a layer of silicon dioxide doped with an impurity of opposite conductivity type on the gate electrode layer and on the surface of the single crystal layer except where the channel of a MOSFET is to be located, diffusing dopant from the doped oxide layer into the gate electrode layer, and into the single crystal layer to form source and drain regions of the transistors, depositing a layer of gate insulating material on the channel region of the MOSFET, and depositing metal on the source and drain regions and on the gates of both transistors.

Switching circuit utilizing gate controlled switching device

Abstract: A switching circuit which utilizes a gate controlled switching device (GCS) or thyristor of the gate turn-off type has its gate connected with a series connection of another switching element and a voltage source and with a current supplying means arranged in parallel to the series connection. The other switching element, which may be a GCS or transistor, has its conductivity controlled by a control signal applied thereto, and the gate controlled switching device is supplied with a turn-off gate current from the voltage source through such other switching element when the latter is conductive, whereas the gate controlled switching device is supplied with a turn-on gate current from the current supplying means when the other switching element is non-conductive.

Self-aligned maskless chan stops for IGFET integrated circuits

Abstract: Many IGFET integrated circuits incorporate a region of enhanced doping under the field oxide to eliminate the possibility of spurious inversion layers causing leakage between devices. Using chemical predeposition technology, this typically requires a photolithographic step to define the region of enhanced doping. This paper describes a structure in which a nonselective implantation that forms an enhanced doping over the entire wafer is selectively compensated through windows patterned in the field oxide to form gate oxide regions. Threshold voltage control is excellent and identical to control devices fabricated without chan stops. The channel hole mobility is normal and no undesirable effects have been observed if care is exercised in controlling the implanted doses. MOS characteristics are normal and are not affected by residual ion damage. Typical parameters for p-channel devices are shown for various levels of compensation, resulting in gate threshold voltages ranging from -0.5 →-2.2 V for p-channel devices. The field threshold is -18.V for a 7000 A thick field oxide and hole mobilities range from 190 to 290 cm2/V.s.

Method of making a metal insulator silicon field effect transistor (mis-fet) memory device and the product

Abstract: The present invention relates to the method of making a memory device of the metal insulator silicon field effect transistor structure having a gate region combining a chemically formed thin oxide layer and a second insulating layer, such as silicon nitride, and to the novel product which results from this method. The method entails the step of chemically oxidizing the surface of the silicon channel region by a self-limiting process to form a thin porous oxide, and a nitriding step which is conducted under conditions producing optimum interface traps and minimum initial charge. Both steps lead to highly reproducible devices. The method is readily applied to large arrays of devices, offering ease of manufacture and close device parameter control. One form of the process provides for the production of both memory and read-out devices appropriate in an array.

Non-volatile variable threshold memory cell

Abstract: Disclosed is a method which utilizes an insulated gate fieldeffect semiconductor device having a gate isolation comprised of at least two different gate isolation materials as a programmable non-volatile memory. Writing into the memory is accomplished by increasing the threshold voltage from its intrinsic device level to a second more positive level by trapping charges of one polarity in the gate isolation layers. Erasing the memory is accomplished by injecting into the gate isolation layers charges of opposite polarity, thereby neutralizing the previously stored charge and causing the modified device threshold voltage to return to substantially the intrinsic value.

Field effect transistor structure for minimizing parasitic inversion and process for fabricating

Abstract: A process for fabricating a field effect transistor having minimal parasitic inversion wherein a field layer of insulating material is formed on a monocrystalline substrate having spaced source and drain regions, an opening formed in the field layer over the gate region, and the body bombarded with impurity ions of the same type as the background doping of the semiconductor body, the bombarding done at an energy sufficient to traverse the field insulation layer to produce an increased concentration of impurity ions just beneath the interface of the semiconductor body and field oxide, and a buried layer of impurity in the gate region.

Threshold adjustment of N-channel enhancement mode FETs by ion implantation

Abstract: Ion implantation of11B+directly into the channel region was used to adjust the threshold voltage of n-channel enhancement mode FETs. Implantation was performed through a 500A gate oxide grown during a standard four-mask FET process. Threshold voltage shift was determined as a function of implant dose and energy by measuring the difference in threshold voltage between implanted and unimplanted devices on the same wafer. Threshold voltage shift varied sublinearly with implant dose. These are believed to be the first results reported accurate enough to show this effect. Threshold voltage shift for a given dose is also reduced as implant energy (or channel depth) is increased. These results are easily understood in terms of a simple model in which the collapse of the depletion region at inversion, due to the additional doping in the channel, partially compensates for this additional doping. Data are compared with a numerical solution that for the first time fully accounts for the nonuniform doping profile, with excellent agreement.

Bootstrap circuit employing insulated gate transistors

Abstract: A bootstrap circuit employing insulated gate transistors comprises a load element connected at one end to a voltage source, an insulated gate transistor connected between the other end of the load element and ground, a load element connected between the voltage source and a gate electrode of an insulated gate transistor at the following stage, and a capacitor connected between the juncture of the first-mentioned load and the first-mentioned transistor. A clock pulse is applied to a gate electrode of the first-mentioned transistor, so that the output potential of a push-pull buffer circuit, for example, which includes the bootstrap circuit may be held high without being severely subjected to the condition that the output impedance of the clock pulse source be low.

Method for making the self-aligned gate contact of a semiconductor device

Abstract: A self-aligned gate contact of a semiconductor device is made without etching the semiconductor member during the gate contact forming step. A metal layer for forming contacts of the semiconductor device is deposited on a major surface of the semiconductor member and thereafter overlaid with a resist layer. A window pattern corresponding to the desired gate contact is formed in the resist layer, and the metal layer is undercut and removed adjacent the window pattern to expose portions of the major surface of the semiconductor member and to form overhanging portions of the resist layer adjacent the window pattern. Simultaneously with the undercutting, at least portions of contacts of the semiconductor device are formed in the metal layer. The desired gate contact is then self-aligned on the major surface by deposition through the window pattern in the resist layer. The method is particularly useful in making Schottky barrier gate field-effect transistors with high frequency capability, which requires minimal distance between source and drain contacts with an electrically separate Schottky barrier gate contact therebetween.

Annealing to control gate sensitivity of gated semiconductor devices

Abstract: The gate sensitivity of a gated semiconductor device such as a thyristor or transistor is decreased with precision without significantly changing certain other electrical characteristics of the device. Conducting portions of the device are first masked against irradiation and then gating portions of the device are selectively irradiated to a high level with a suitable radiation such as electron radiation to greatly increase the gate current to fire (Ig). The device is then indiscriminately or selectively annealed, preferably while monitoring the gate current, to reduce the gate current to fire (Ig) to a desired value.

Field-effect gridistor-type transistor structure

Abstract: A field-effect semiconductor structure of the gridistor type comprises a wafer of semiconductor material of one type of conductivity having an upper and a lower surfaces, a drain electrode on said lower surface of the wafer, a gate of semiconductor material of the opposite type of conductivity embedded in the wafer, a plurality of conductive channels perpendicular to and surrounded by said gate, said gate being covered with an epitaxiably deposited layer of the said type of conductivity. A frame surrounding the gate and frame bars dividing the gate into compartments are embedded in the wafer and in ohmic contact with the gate. In order not to extend the gate thickness during the process of heightening the frame from its embedded level up to the upper surface, a pit is sunk opposite the frame and the gate contact is taken on the frame at the bottom of the pit. The gate, frame and frame bars have their middle part formed in a low-resistivity semiconductor layer and their lateral parts formed respectively in two high-resistivity semiconductor layers adjacent to and on both sides of the low resistivity layer.

Matched pair of enhancement mode mos transistors

Abstract: A method and apparatus for matching the DC current-voltage characteristics of two MOS enhancement mode transistors. The method interdigitates pieces of two transistors in such a way that the average characteristic of the two transistors is the same while conserving as much area as possible. The matching of the average characteristic of the two transistors is due to a topological layout that preserves the gates of the transistors in close proximity to one another. The gate oxide for both transistors is deposited in one long continuous strip. The gate electrodes for the two devices are divided into several parallel connected pieces. The pieces of each gate are deposited in alternating positions along the length of the gate oxide. The interconnection of the gates, sources, and drains are then made in such a way so as to keep the diffused viae as short as possible thus minimizing the series drain and source resistances. The topology disclosed herein also obviates the need for two layers of metalization.

Method of manufacturing a field-effect transistor

Abstract: The method for making an improved field-effect transistor by using a thick insulating layer, the thickness of which is larger than the diffusion length of the impurity forming the base region in a following process step, as a mask for successive diffusion of two different impurities of different conductivity types and by using a portion of the thick insulating layer on the drain region as a portion of the gate insulating layer to reduce a parastic capacitance between the gate and the drain.