Showing papers on "Gate oxide published in 1977"

Triple layer polysilicon cell

Abstract: A triple layer polysilicon cell for use in an electrically erasable PROM or for a discretionary circuit connector is described. Tunneling is employed to transfer charge to a floating gate from a programming gate and also to transfer charge from the floating gate to an erasing gate. Through light doping steps, the first layer of polysilicon (programming gate) and a second layer of polysilicon (floating gate) include rough surfaces. These rough surfaces provide enhanced electric fields which allow tunneling through relatively thick oxides.

Insulated gate field effect transistor

Abstract: An insulated gate field effect transistor is formed of a drain region of a first conductivity type which faces both of the major surfaces of a semiconductor substrate, a frame region of a second conductivity type which faces the one major surface of the semiconductor substrate, a base region of the second conductivity type which faces the one major surface and is connected to the frame region, a PN junction being formed between the base region and the drain region, and a source region of the first conductivity type which faces the one major surface and is formed in the base region as if being surrounded thereby. The insulated gate field effect transistor is also provided with a source electrode which short-circuits the frame region and the source region, a drain electrode which is provided on the drain region facing the other major surface of the substrate, and a gate electrode which is provided on the base region facing the one major surface through a gate insulating layer.

Method of making a high density floating gate electrically programmable ROM

Abstract: An N-channel, double level polysilicon, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level polysilicon is then applied as strips overlying the original strips.

Effect of electron trapping on IGFET characteristics

Abstract: At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO2 layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO2/Si3N4 as gate insulator, electron trapping is completely dominated by the Si3N4 layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO2 as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.

Insulated gate field-effect transistor read-only memory array

Abstract: An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain. Embodiments of such an array are shown and may be utilized as a ROM, PROM and EPROM.

Chemical-sensitive field-effect transistor

Abstract: The invention relates to an insulated-gate field effect transistor which is adapted for detecting and measuring various chemical properties such as ion activity in a solution. The device has a chemically sensitive layer which overlies a portion of a substrate other than that covered by the gate insulator. When this chemically sensitive layer is exposed to a solution or other substance, the electric field in the substrate is modified which changes the conductance of the channel between a source region and a drain region. The change in conductance is related to the chemical exposure and can be detected with a current meter.

Electrically erasable non-volatile semiconductor memory

Abstract: A non-volatile semiconductor storage device comprising a dual gate field effect transistor in which an electrically floating gate acts as a charge storage medium. An insulating layer of an appropriate dielectric material separates the floating gate from the active portion of the transistor. A predetermined section of this insulating layer is relatively thin to permit this section of the floating gate to be relatively close to a corresponding predetermined section of the transistor, thus facilitating the transfer of charges between the transistor substrate and the gate. When charges reach the floating gate either through tunneling or avalanche injection, they are entrapped and stored there, thus providing memory in the structure. That is, the electric field induced by these charges is maintained in the transistor even after the field inducing force is removed. Erasing is achieved by removing the charges from the floating gate by reverse tunneling through the relatively thinner insulator region.

Two and three mask process for IGFET fabrication

Abstract: Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level. The first mask of the two-mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions. After forming a thin oxide layer in these windows, the wafer is coated with successive layers of polysilicon and silicon nitride. Then, a second masking operation yields a pattern out of the polysilicon-nitride layer including gate electrodes and a top-lying interconnection level which abuts to openings etched through the thin oxide layer. Doping impurities are diffused therethrough to form source and drain regions and crossunders. After etching the nitride layer a silicide forming metal is deposited and sintered to form a silicide layer on all exposed silicon surfaces lowering the sheet resistance of the polysilicon layer and joining the interconnection pattern with the source and drain regions. The process is completed by removing the remaining unreacted metal using a maskless aqua regia etch.

Electrically programmable and electrically erasable MOS memory cell

Abstract: An MOS memory cell which includes a floating gate charged from the substrate by avalanche injection. Charge is removed from the floating gate to an erasing gate by tunneling. Sharp edges on the polycrystalline silicon floating gate provide an enhanced electric field to overcome the silicon/silicon oxide barrier, thus permitting charge to be transferred from the floating gate to the erasing gate.

Method of making an insulated gate field effect transistor by implanted double counterdoping

Abstract: An insulated gate field effect transistor having spaced highly doped source and drain regions with less highly doped source and drain extensions, which define the ends of the channel of the transistor, has both the source and drain extensions and the channel of the transistor defined in a controllable manner by the steps of forming a continuous zone of the same conductivity type as the source and drain regions in the space between these two regions and then counterdoping a portion of this layer.

Process for minimum overlap silicon gate devices

Abstract: A method of manufacturing a silicon gate MIS device providing automatic formation and alignment of the gate structure during formation of adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-- typically oxide and silicon-- are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to a predetermined size beneath the overhanging mask. A deposition mask in the form of the photoresist mask or the gate silicon oxide and which is of the same size as the photoresist mask, is used to control the deposition of impurities within predetermined surface areas of the substrate which are spaced a predetermined distance from the silicon gate boundaries. By diffusion, the impurities are driven into the substrate to the desired depth to complete the source and drain, which are thereby driven laterally into coincidence with the gate boundaries. The aligned, non-overlapping relationship of the gate structure with the source and drain minimizes gate overlap capacitance.

High density N-channel silicon gate read only memory

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Gate electrode for MNOS semiconductor memory device

Abstract: Optimized switching and retention characteristics of an MNOS memory device are obtained by using as a gate electrode material either metals or semi-metals having a high work function, in conjunction with a gate dielectric layer having a low density of trapping states throughout its volume. The preferred gate electrode materials are either titanium or p + -doped polycrystalline silicon.

Mos type semiconductor device and its manufacture

Abstract: PURPOSE: To manufacture the short channel MOS, by providing the source and drain with self alignment, after providing the insulation film with vapor phase growing only on the gate side surface and its vicinity. CONSTITUTION: Field oxide film 2, gate oxide film 3, and poly-Si gate 4' are formed on the p type Si substrate 1, and the CVD oyxide film 6 is uniformly de- posited. Next, when etching gas is vertically incident, the etching speed is slow at the gate side surface 4'b. When the film 3 and the film 6 of the gate upper surface 4'a are removed and etching is stopped, fine insulation film pattern 6' covering only the side surface 4' and the gate film 3 near it is formed and the width W is the thickness of the film 6 on the side surface 4'b. After that, diffusion is made so that the spread 1 to the side of the n type source and drain 7 and 8 is greater than the width w of the film 6', CVD oxide film 9 is deposited and electrodes 10 to 12 are provided by performing selective opening. With this constitution, without lower- ing the ric dielectric strength between the gate and the source and drain, short channel MOS can be formed. COPYRIGHT: (C)1979,JPO&Japio

Junction gate type gaas field-effect transistor and method of forming

Abstract: The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga 1-y Al y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.

Schottky-gate field-effect transistor and fabrication process therefor

Abstract: The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no post-implantation annealing.

Method of making FET containing stacked gates

Abstract: A field effect transistor (FET) comprising a floating gate and a control gate in a stacked relationship with each other and being self-aligned with each other and self-aligned with respect to source and drain regions. The fabrication technique employed comprises delineating both the floating gate and control gate in the same lithographic masking step.

Grooved Gate MOSFET

Abstract: Grooved Gate type MOS FET's which realize a short channel device with high punch-through breakdown voltage and little threshold voltage (VT) fluctuation, are fabricated by using a promising photoresist technique. A proposed, self-aligned gate MOS FET structure (Grooved Gate MOS FET) is based on two-dimensional analyses of short channel devices. A characteristic feature of the device is negative source and drain junction depth. The fabricated 21 stage ring oscillator displays a high circuit performance for delay and power product of 0.12 pJ.

Method for forming ion-implanted self-aligned gate structure by controlled ion scattering

Abstract: A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents--typically oxide and silicon--are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.

Gapped gate charge-flow transistor with a thin film sensor having two modes of conduction within the gapped gate used to sense a property of the ambient environment

Abstract: A charge-flow transistor having a gapped gate electrode and a thin-film sensor material in the gap, which sensor material is sensitive to a property of the ambient environment and has a surface conductance that differs substantially from the bulk conductance thereof. The charge-flow transistor is shown as part of an instrument operable to measure said property.

Method for manufacturing complementary insulated gate field effect transistors

Abstract: Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

Self-protection against breakover turn-on failure in thyristors through selective base lifetime control

Abstract: A thyristor is protected against voltage breakover turn-on failure by selective control of the minority charge carrier lifetime in the base region and in the gate region to establish a predictable location of the voltage breakover turn-on in the gate region. Carrier lifetime modification in the selected gate region is achieved by shielding the gate region during electron irradiation of the high-lifetime silicon substrate to protect against lifetime-killing radiation defect centers, by annealling the gate region after electron irradiation to a temperature threshold known to eliminate the radiation-induced defects, or by introducing lifetime killing defects, such as gold or platinum, external to the gate region, typically by selective diffusion or localized ion implantation. As a result, a locally higher gate sub-transistor gain thyristor is attained, so that the turn-on criterion, the unity product of the base transport factor and the avalanche multiplication factor, is established at a lower voltage in the gate region than elsewhere in the thyristor device.

Double ion implanted V-MOS technology

Abstract: An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.

Lithographic offset alignment techniques for RAM fabrication

Abstract: Lithographic offset alignment techniques for MOS dynamic RAM memory cell fabrication to enable increased packing density while maintaining the minimum patterned geometry. Technique of cell fabrication involves initial oxidation of P-type silicon, for example, followed by silicon nitride deposition. Thereafter, moats are etched using the composite silicon dioxide-silicon nitride layers, followed by boron deposition or ion implantation in regions of the silicon substrate exposed by the etching treatment. The moats are then filled by oxidation to form a large field deposit of silicon dioxide extending above the level of the oxide layer in the regions where the moats were formed. The remaining composite silicon dioxide-silicon nitride layers are then removed, followed by gate oxidation. A P-type ion implant is provided beneath the thin oxide region between the regions to be overlaid by a polysilicon electrode and the thick field oxide of the succeeding cell. Thereafter, polysilicon is deposited and patterned, the patterned polysilicon electrode covering a fraction of the P-type implant. The gate oxide is then removed by etching, followed by N+ diffusion or ion implantation in the exposed region of the P-type implant to define a bit line having a length less than the minimum patterned geometry. Oxide is then applied by chemical vapor deposition, followed by a deposit of metal or polysilicon and patterning as required. The offset alignment of the polysilicon electrode with respect to the P-type implant creates the smaller dimension for the sense line. A fabrication technique for the CC RAM having an implanted storage region and a fabrication technique for a double-level polysilicon cell both using offset alignment techniques are also disclosed.

A field effect transistor logic gate having depletion mode and enhancement mode transistors

Abstract: A logic gate having a first depletion mode field effect transistor with a gate electrode adapted for coupling to a control signal source, a second depletion mode field effect transistor and an enhancement mode field effect transistor, such enhancement mode field effect transistor being serially connected to the second depletion mode transistor. The second depletion mode transistor and the enhancement field effect transistor are fed by the first depletion mode transistor. One of such serially connected transistors has a Schottky gate contact. With such arrangement the logic gate includes a "complementary" pair of relatively short channel length devices fed by a relatively short channel length device to provide low static power dissipation and large output capacitance drive capability.

Method for making an insulated gate field effect transistor utilizing a silicon gate and silicide interconnection vias

Abstract: The invention disclosed pertains to a method for the manufacture of an integrated insulated gate field effect transistor semiconductor device wherein a silicon gate structure is simultaneously formed with a composite layer of silicon and a conductive silicide forming metal which upon subsequent annealing forms a conductive metallic silicide compound within the via interconnection means. The aforesaid structure is accomplished utilizing a photoresist lift-off technique as a masking material as well as a substance per se or in combination with other materials to define evaporative conductive metal dimensions on a diffused silicon substrate.

Field effect transistor with a short channel length

Abstract: of the Disclosure A field effect transistor with a MIS gate arrangement having a source and drain formed in a semiconductor body and including an electrically con-ductive region additionally provided which lies beneath the source zone and which has a conductivity opposite to and/or electrical conductivity which is higher than the semiconductor body which surrounds the zone and in which in the controllable field effect gate the electrically conductive zone is spaced a distance from the gate and the boundary surface and wherein the gate insulation layer projects laterally a space relative to the source zone which is approximately 1 to 10 times the thickness of the gate insulation layer and the distance from the gate arrangement to the boundary surface is 1 to 5 times the thickness.

Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors

Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Abstract: Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Semiconductor controlled luminescent device

Abstract: A p type semiconductor gate layer is buried in an N type semiconductor cathode layer to encircle a channel through which the forward current of a luminescent PN junction passes. A reverse voltage is applied to the gate layer to spread a depletion layer in the channel to control the forward current and therefore the emission of light. The gate layer may be disposed on that surface of the cathode layer remote from the luminescent PN junction with a groove disposed the other surface of the cathode layer to narrow the channel.