scispace - formally typeset
Search or ask a question

Showing papers on "Gate oxide published in 1979"


Journal ArticleDOI
TL;DR: In this article, the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's is discussed, and the effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data.
Abstract: This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

184 citations


Patent
04 Sep 1979
TL;DR: In this paper, a simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect, which is similar to the one described in this paper.
Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

100 citations


Patent
18 Jul 1979
TL;DR: In this paper, an integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of a multilayer insulating layer comprised of a storage layer and a "blocking" layer.
Abstract: An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

92 citations


Journal ArticleDOI
H. Masuda1, Masaaki Nakai1, M. Kubo1
TL;DR: In this article, the authors investigated the practical limitations of minimum-size MOS-LSI devices through measurement of experimental devices and concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V.
Abstract: Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

88 citations


Journal ArticleDOI
P.E. Cottrell1, R.R. Troutman1, T.H. Ning1
TL;DR: In this article, the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs is discussed, and the effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data.
Abstract: The authors discuss the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

79 citations


Patent
08 May 1979
TL;DR: In this article, a high-voltage circuit for insulated gate field effect transistors (MOSFETs) is provided, where two MOSFets are connected in series, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFCET.
Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.

76 citations


Patent
05 Jan 1979
TL;DR: In this article, a nonvolatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide.
Abstract: A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

59 citations


Patent
28 Jun 1979
TL;DR: In this paper, a self-aligned MOS transistor is constructed using undercut etching of a polycrystalline silicon gate electrode, which allows the source and drain regions to be selfaligned with and closely spaced to the gate electrode.
Abstract: A self-aligned MOS transistor having improved operating characteristics and higher packing density and a method for fabricating the device. Resistance of the gate electrode is reduced substantially by forming the electrode of a metal silicide. Resistance of the source and drain regions is likewise reduced substantially by forming a metal silicide in the doped junction region which allows those regions to be smaller and to require less area. The silicided source and drain regions are self-aligned with and closely spaced to the silicided gate electrode. This is provided by a process which utilizes and makes possible an undercut etching of a polycrystalline silicon gate electrode.

58 citations


Journal ArticleDOI
G.W. Taylor1
TL;DR: In this article, a model is presented to describe the above-threshold characteristics of short-channel Insulated Gate Field Effect Transistor (IGFET) when they are affected by the proximity of the source and drain junctions.
Abstract: In a short-channel Insulated Gate Field Effect Transistor (IGFET), a significant fraction of the electric field lines associated with the depleted region under the gate are terminated on the source and drain junctions. In this situation the two-dimensional sharing of the depleted substrate charge between the source, drain and gate terminals, has a dramatic effect on the device behaviour. A model is presented to describe the above-threshold characteristics of short-channel IGFETS when they are affected by the proximity of the source and drain junctions. The analytical forms allow a continuous description of the drain current from subthreshold to above threshold conduction. The model takes into account the fact that the device may be turned on by the drain voltage rather than by the gate voltage; in addition, it describes naturally the enhanced drain conductance commonly encountered in short-channel devices. The description includes both the linear and saturation regions over the complete range of drain and substrate voltages and for gate voltages below the value where channel-drain junction interactions become important or velocity saturation sets in. The model therefore provides an analytical description for a short-channel IGFET in the voltage regime where high-field effects in the channel do not significantly effect the current flow. The results indicate that the dominant effects for this region of operation in a short-channel device may be represented by the use of a drain-voltage and geometry-dependent threshold voltage. In the saturation region, the effects of the threshold variations are reflected in the parameter VSAT, the saturation voltage. The principle features of the model are verified by a detailed comparison with short-channel devices.

55 citations


Patent
13 Nov 1979
TL;DR: In this paper, an electrically programmable memory array of the floating gate type with a high coupling ratio is made by a DMOS process, which allows the edges of floating gates to be self-aligned with the edge of the control gates and produces improved characteristics in the form of higher gain and lower body effect.
Abstract: An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a DMOS process which allows the edges of the floating gates to be self-aligned with the edges of the control gates and produces improved characteristics in the form of higher gain and lower body effect. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. Double-diffused regions are formed on one or both sides of the channel, also beneath thick oxide, instead of using a P+ tank. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased and the degradation in the cell performance usually caused by the P+ tank is avoided.

53 citations


Patent
02 Jan 1979
TL;DR: In this paper, an electrically programmable memory array is made by a process in which the memory elements are capacitor devices formed in anisotropic etched V-grooves to provide enhanced dielectric breakdown at the apex of the groove.
Abstract: An electrically programmable memory array is made by a process in which the memory elements are capacitor devices formed in anisotropically etched V-grooves to provide enhanced dielectric breakdown at the apex of the groove. After breakdown, a cell exhibits a low resistance to a grounded substrate. Access transistors in series with the memory elements have control gates which also form address lines. The oxide thickness in the V-groove may be thinner than the gate oxide thickness for the access transistor providing a lower programming voltage. These factors provide a very small high speed device.

Journal ArticleDOI
TL;DR: In this article, a metal-insulator-semiconductor field effect transistors (m.i.f.t.s) have been fabricated using c.c.v.d.
Abstract: InP metal-insulator-semiconductor field-effect transistors (m.i.s.f.e.t.s) have been fabricated using c.v.d. Al2O3 as the gate insulator and the sulphur-diffusion process for source and drain. The n-channel inversion-mode device exhibits normally off behaviour. A maximum d.c. transconductance gm of 10 mS (87 mS/mm of gate width) has been obtained.

Patent
Robert M. Jecmen1
05 Feb 1979
TL;DR: In this paper, a method for substantially reducing the overlap between a gate and the source and drain regions of a field effect transistor is described, where a small amount of dopant is implanted through the overhangs providing a low concentration of dopamine in alignment with the gate.
Abstract: A process for substantially reducing the overlap between a gate and the source and drain regions of a field-effect transistor is disclosed. Lateral etching of a polysilicon gate provides overhangs which extend from a gate masking member. Source/drain regions are formed by ion implanting through the gate oxide layer. A small amount of dopant is implanted through the overhangs providing a low concentration of dopant in alignment with the gate. During subsequent processing, this low concentration of dopant does not substantially diffuse as do regions of higher concentration. Significant reduction in Miller capacitance is obtained along with improved punch-through characteristics.

Patent
06 Nov 1979
TL;DR: In this paper, a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired is presented.
Abstract: The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

Patent
17 Sep 1979
TL;DR: In this article, an electrically programmable memory array with a high coupling ratio is made by a process which allows the edges of the floating gates to be self-aligned with the edge of the control gates.
Abstract: An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a process which allows the edges of the floating gates to be self-aligned with the edges of the control gates. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased by extending the floating gate out over the source and drain since the thick oxide reduces coupling from the floating gate to the source and drain.

Patent
10 Dec 1979
TL;DR: In this paper, a stack gate type nonvolatile memory device is used to reduce the number of contacts by taking the substrate as the source and to increase the degree of integration, by obtaining sufficient gm, small junction capacitance and high dielectric strength, through the use of DSA technology.
Abstract: PURPOSE:To reduce the number of contacts by taking the substrate as the source and to increase the degree of integration, by obtaining sufficient gm, small junction capacitance and high dielectric strength, through the use of DSA technology to the stack gate type non-volatile memory device. CONSTITUTION:The N epitaxial layer 28 is laminated on the N type substrate 27, and oxide film 32, nitride film 31, and oxide film 30 are laminated. The films 32 to 30 are opened, B diffusion layer 44 is formed, and field oxide film 43 and gate oxide film 39 are formed. The polycrystal Si floating gate is selectively formed, and the polycrystal Si control gate 42 is formed via the second gate oxide film 40. Next, ion injection is selectively made, and P layer 35 is formed deeper than the N layer 28. The N source 37 and drain 38 are formed inside and outside the layer 35, and the electrode 45 is attached. Since the N layer 28 is in contact with the layer 35 being channel, the dielectric strength is high, junction capacitance is small, and since the current flows from the source 37 to the substrate 27, the source connection hole and electrode are unnecessary, to increase the degree of integration.

Journal ArticleDOI
J.M. Aitken1
TL;DR: In this article, the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined and it is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides.
Abstract: In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 1010cm-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm2. Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 1010cm-2.

Patent
22 Feb 1979
TL;DR: In this article, an electrically reprogrammable non-volatile memory (NVM) device with complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n-type substrate is described.
Abstract: An electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n - -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential. This device enables writing control to be performed using a logical signal of the order of one volt, read-out being also performed with a low voltage value, with low energy consumption. Erasure of information can be performed electrically and the retention time is of several years.

Patent
15 Oct 1979
TL;DR: A silicon-on-sapphire semiconductor structure was proposed in this article, in which a silicon nitride layer is provided over the oxide layer, which acts to prevent gate oxide breakdown.
Abstract: A silicon-on-sapphire semiconductor structure, and method of fabricating such structure, in which a silicon nitride layer is provided over the oxide layer. The silicon nitride layer is disposed over the upper edge of the silicon island, and acts to prevent gate oxide breakdown.

Journal ArticleDOI
TL;DR: In this article, the authors describe a process based on photolithography and chemical etching which avoids this interruption to manufacture, and demonstrate that the resulting TFTs can operate at up to more than 100 V.

Patent
19 Sep 1979
TL;DR: In this article, a complementary type MOS transistor device was proposed, which has source, drain and gate regions formed in the n-well region of a p-type semiconductor layer.
Abstract: A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions formed in the n-well region which is formed in the surface area of a p-type semiconductor layer and an n-channel MOS transistor having source, drain and gate regions formed in said semiconductor layer. The semiconductor layer is formed on an n-type semiconductor body and a reverse bias voltage is applied between the semiconductor layer and the semiconductor substrate.

Patent
05 Jan 1979
TL;DR: In this paper, a nonvolatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application of high voltage across the source and drain so that hot electrons traverse the gate oxide.
Abstract: A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application of high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. An over-erase sensor transistor separate from the memory transistor prevents the floating gate from being discharged below a point where the memory transistor will be depletion mode.

Patent
28 Dec 1979
TL;DR: In this article, a gate drive pulse is applied to the gate of the field effect transistor (Q2) on a common potential point side, and a parallel connection circuit having a first resistor (R3) and a first capacitor (C3) is coupled between the gate and the other field effect transistors (Q1) on the common potential side.
Abstract: In a circuit arrangement having a plurality of field effect transistors which are connected in series and operate simultaneously, the circuit arrangement is free from restriction of an operating frequency and it is not necessary to provide an individual power source for gate biasing, so that the construction of the circuit arrangement is simplified and the cost is reduced A gate drive pulse is applied to the gate of the field effect transistor (Q2) on a common potential point side A parallel connection circuit having a first resistor (R3) and a first capacitor (C3) is coupled between the gate of the other field effect transistor (Q1) and the common potential point side A parallel connection circuit having a second resistor (R4) and a second capacitor (C4) is coupled between the first electrode (eg drain) and the gate of the other field effect transistor A capacitance of the first capacitor is larger than that of the second capacitor, so that the other field effect transistor is sufficiently shifted to a conductive state when the gate drive pulse is applied to the field effect transistor on the common potential side

Patent
22 Nov 1979
TL;DR: In this article, a perforated MOS transistor is used as the gate to detect the presence of ions, atoms and molecules in gases or solutions, which can be measured as a voltage, threshold voltage or capacitance change.
Abstract: A device for the detection of the presence of ions, atoms and molecules in gases or solutions consists of a semiconductor substrate (1) with an insulating coating (2) (which can be designed as a pn-junction with reversed polarity in the substrate) and a conductive layer. (3)The latter has perforations so that the ions can come into contact with both coatings. If designed as an MOS transistor, the substrate includes doped regions (9) of the opposite conductivity as drain and source, and the perforated coating is used as the gate. The gases or solutions can thus reach the insulator boundary and produce under the gate a change of the work function which can be measured as a voltage, threshold voltage or capacitance change.

Patent
26 Sep 1979
TL;DR: In this article, a method for fabricating an MOS integrated circuit having a refractory metal gate structure is described, which includes the formation of an insulating layer and a conductive refractive metal layer on a substrate, followed by the selective removal of portions of these layers to define the locations of source, drain, and other diffused regions.
Abstract: A method for fabricating an MOS integrated circuit having a refractory metal gate structure includes the formation of an insulating layer and a conductive refractory metal layer on a substrate, followed by the selective removal of portions of these layers to define the locations of source, drain, and other diffused regions. After the diffusion or implantation of the drain and source regions, using the refractory metal as a mask, the refractory metal, other than at the gate regions, is removed, and the portion of the underlying insulating layer that is thereby exposed is then etched away. An oxidizing step is performed to form a thick oxide region at those areas of the substrate not covered by the remaining portions of the refractory metal layer. Also disclosed is an MOS refractory metal gate MOS device fabricated by the method.

Patent
26 Oct 1979
TL;DR: In this article, an integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors.
Abstract: An integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer. High value polysilicon resistors are formed over an outer protective silicon dioxide layer of the silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors. The process for making the integrated circuit includes forming a sheet of polysilicon over the entire wafer surface, performing the ion implantation and etching away all but the desired resistor portions of the polysilicon. It also includes heating the wafer to simultaneously anneal the ion implanted polysilicon, form the gate oxide, thicken the oxide over the emitters, and cover the resistor body with a thin protective oxide film.

Patent
Tamaki Sawazaki1
26 Feb 1979
TL;DR: In this article, a semiconductor substrate of an N type is formed partially of a well region of a P type by means of a first ion implantation process, then subjected to selective diffusion to form source and drain regions of the original substrate, whereby a first insulated gate field effect transistor is formed, and further subjected to a selective diffusion in the well to form a second insulated gate FD transistor.
Abstract: A semiconductor substrate of an N type is formed partially of a well region of a P type by means of a first ion implantation process, then subjected to selective diffusion to form source and drain regions of a P type on the surface of the original substrate, whereby a first insulated gate field effect transistor is formed, and further subjected to selective diffusion to form source and drain region of an N type in the well, whereby a second insulated gate field effect transistor is formed. The semiconductor device is then subjected to a second ion implantation process such that an impurity of an N type is simultaneously ion implanted in the substrate surface surrounding at least the first field effect transistor and the channel region of the second field effect transistor, and is then subjected to formation of an insulation film such that a thick insulation film is formed on the surface of the original substrate and the well, while a thin gate insulation film is formed on the channel regions of the first and second field effect transistors. Then the device is further subjected to a third ion implantation process such that an impurity of a P type is ion planted to the channel regions of the first and second field effect transistors through the thin gate insulation films.

Patent
Meguro Satoshi1
05 Jan 1979
TL;DR: In this paper, a gate electrode is formed over a channel region between the source layer and the drain layer in the substrate surface through an interposed gate insulating film, wherein the semiconductor substrate is formed with selectively buried insulation films between the sources and drain layers and the channel portion in thickness greater than that of the gate insulator film and further under the selected insulating films formed with a first region of the same conduction type as that of a source layer insulating for connecting the channels to each other, the second region having an impurity concentration greater than the drain region
Abstract: Disclosed is a MIS type semiconductor device in which a source and a drain layer are selectively formed in a surface of a semiconductor substrate while a gate electrode is formed over a channel region between the source layer and the drain layer in the substrate surface through an interposed gate insulating film, wherein the semiconductor substrate is formed with selectively buried insulation films between the source and drain layers and the channel portion in thickness greater than that of the gate insulating film and further under the selected insulating films formed with a first region of the same conduction type as that of the source layer insulating for connecting the channel portion and the source layer to each other and with a second region of the same conduction type as that of the drain layer for connecting the drain layer and the channel portion to each other, the second region having an impurity concentration greater than that of the drain region, and the gate electrode is formed as extending over the selected insulating films. The second region underlying the selectively buried thick film functions as a saturatable resistance element to increase the voltage which the device can withstand. The channel length is unvariably determined by the distance between the first and the second region. No dielectric breakdown will occur at the end portions of the gate electrode extending over the selective insulating films.

Patent
15 May 1979
TL;DR: In this paper, a high sensitivity photo-electric converter is provided by electrically isolating the gate region of a static induction transistor which exhibits non-saturating current versus voltage characteristic.
Abstract: A high sensitivity semiconductor photo-electric converter is provided by electrically isolating the gate region of a static induction transistor which exhibits non-saturating current versus voltage characteristic. Optically ionized minority carriers are stored in the gate region to control the potential thereof. A semiconductor gate region provided with a insulated gate is very effective to enhance the dynamic range of the converter. Non-saturating characteristic enables enlargement of the output current simply by increasing the drain voltage. A high-speed and high sensitivity image pick-up device can be materialized by integrating a multiplicity of the static induction type photo-electric converter elements. A switching transistor may be merged in the gate region of each photo-electric converter element to enhance the operation speed of the image pick-up device.

Journal ArticleDOI
TL;DR: In this article, the gate switching characteristics of a p + substrate containing an epitaxial n -layer were investigated. But the gate voltage was not measured. And the gate efficiencies were not analyzed.
Abstract: The device described here comprises a p + substrate containing an epitaxial n -layer, on the surface of which is grown a thin (∼50 A) tunnel oxide. A metal cathode is deposited on the oxide surface, and a metal anode on the back side of the p + substrate. A third terminal, the gate electrode, is connected to the n epilayer to provide for biasing the n - p + junction. The I-V characteristic exhibit two stable states: a high-impedance state and a low-impedance state which are separated by a negative-resistance region. The high-impedance state is stable for applied voltages up to the intrinsic threshold voltage, V s . When the switching voltage is exceeded, the device switches rapidly to the low-impendance state, which is characterized by a current that increases with little increase in the voltage across the device. The switching voltage may be reduced below V s by current or voltage biasing of the n - p + junction by means of the gate electrode. Gate efficiencies, the ratio of the change in switching voltage with d.c. gate voltage or current, of 10 V/V and 1.0 V/μA have been observed. Pulsed gate measurements are also presented, and it found that for pulse widths down to 0.1 μs the gate switching characteristics follow the d.c. characteristics. For pulse widths less than 0.1 μs the gate efficiencies are degraded. Suggestions for improving the device characteristics and the turn-on and turn-off time of the device and device reliability are discussed.