Showing papers on "Gate oxide published in 1981"

Hot-electron injection into the oxide in n-channel MOS devices

Abstract: In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.

Fabrication process of sub-micrometer channel length MOSFETs

Abstract: Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

Threshold-voltage instability in MOSFET's due to channel hot-hole emission

Abstract: Hydrogen introduced and trapped in the gate oxide of MOSFET's by the silicon-nitride capping process can be activated by emitted holes from the MOSFET channel to produce a large threshold-voltage shift. This effect requires avalanche multiplication in the channel for the production of holes when a dc voltage is applied to the gate. For the pulsed-gate case, the magnitude of the threshold-voltage shift depends significantly on the gate-pulse fall time, cycle time, and duty cycle. In both cases the electric field normal to the Si/SiO 2 interface near the drain aids the emission of holes across that interface. A semiquantitative model is proposed which says that holes can recombine at H 2 molecules and release sufficient energy to cause dissociation. The atomic hydrogen created can participate in electrochemical reactions at the gate oxide/channel interface which create nonuniform distributions of trapped charge and interface states along the channel. Model calculations of the time, temperature, and voltage dependences of this threshold instability agree well with measured results.

Method for fabricating MOS device with self-aligned contacts

Abstract: A method for fabricating an integrated circuit semiconductor device comprised of an array of MOSFET elements having self-aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer (30) surrounding openings (99) therein for the MOSFET elements. A gate electrode (38) within each opening is utilized to provide self-registered source (42) and drain (44) regions and is covered on all sides and on its top surface with a gate dielectric layer (46). After the formation of the source-drain regions a relatively thin dielectric protective layer (38) is applied to the entire chip prior to the application of an upper insulative layer (50). When oversized windows are etched in the upper insulative layer, the protective layer prevents etching of the gate dielectric layer (46), thus preventing shorts or leaks between conductive and active areas and providing self-aligned contacts with minimum spacing from adjacent conductive areas (40). With the present method, additional internal protection over prior art devices is provided in MOS devices with source-drain regions formed either by diffusion or ion implantation.

Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Method of manufacturing silicide contacts for CMOS devices

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

Ionization of SiO2 by Heavy Charged Particles

Abstract: Highly ionizing heavy charged particles generate significant charge as they pass through the thin thermally grown gate oxide of a MOSFET device. The amount of charge created by an alpha particle and proton is calculated and the yield of charqes which escape initial recombination is measured. The experimental results are shown to agree with a charge recombination model where an ionization track radius of 30-40 A is assumed. Finally, implications of the findings for single charged particle effects in submicron dimension devices are discussed.

Self-aligned field effect transistor process

Abstract: A method for fabricating a semiconductor [integrated circuit] structure having a sub-micrometer gate length field effect transistor device is described. An isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistors [devices]. A heavily doped conductive layer and an insulator layer are formed thereover. The multilayer structure is etched to result in a patterned conductive layer having substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings in the pattern at the location of the field effect transistor channel. The pattern in the source/drain areas extend over the isolation pattern. A controlled sub-micrometer thickness insulating layer is formed on these vertical sidewalls. The sidewall insulating layer is utilized to controllably reduce the channel length of the field effect transistor. [The sidewall layer is preferably doped with conductive imparting impurities.] The gate dielectric is formed on the channel surface. The source/drain regions [and preferably lightly doped region] are [simultaneously] formed by thermal drive-in from the conductive layer [and sidewall insulating layer respectively]. The desired gate electrode is formed upon the gate dielectric and electrical connections made to the various elements of the field effect transistor devices. [The conductive layer and resulting contacts to said source/drain regions may be composed of polycrystalline silicon, metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.]

Self-refreshing memory cell

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode

Abstract: A vertical MOSFET includes source and gate electrodes on a major semiconductor surface, and a drain electrode on an opposing semiconductor surface. A shield electrode is disposed in proximity to the gate electrode so as to minimize feedback capacitance between the gate electrode and drain region. Additionally, the shield electrode increases the level of space charge limited current that can be supported in the drain region, and minimizes current crowding in the device.

A model of a narrow-width MOSFET including tapered oxide and doping encroachment

Abstract: A closed-form analytical expression is developed to predict the threshold voltage of a narrow-width MOSFET. The analytical expression developed is the first to include the effects of a recessed tapered oxide, the depletion charge under the thick recessed field oxide due to gate contact overlap and field doping encroachment at the channel edges. The theory is compared with experimental results and the agreement is dose.

Semiconductor memory device with peripheral circuits

Abstract: A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

Schottky MOSFET for VLSI

Abstract: Recently MOSFET with Schottky source and drain has been considered an important candidate for VLSI because of its ultra-shallow junctions to minimize short-channel effects, low source and drain series resistances, simplified processes, and the elimination of minority carrier injection into the substrate [1]. We present results of MOSFETs with 300A PtSi as the source and drain contacts. The devices are fabricated on 2 × 1015cm-3, oriented n-Si substrates; and the gate oxide thickness is 250-300A. Long-channel behavior is observed for devices with channel lengths down to 1 µm, in very good agreement with the generalized guide for MOSFET miniaturization[2]. We observe that the output currents are smaller than those for the conventional MOSFETs. This is explained by the potential barrier arising in the gap between the Schottky source contact and the inversion channel. Extensive Arrhenius plots indicate that the gap has a profound effect in enhancing the corner field which in turn can greatly increase the current availability from the source. By reducing the gap to about 100A, the current approaches that as expected from the Pao-Sah theory[3].

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a high-density memory easy to be fined by a method wherein an (n) layer and a (p) layer in a capacitance section are formed by the self-alignment of a gate electrode, mask alignment is omitted, a capacitance electrode is also shaped to the upper section of the gate electrode through SiO2 and mask re-alignment is omitted. CONSTITUTION:The surface of a p-type Si substrate 1 is isolated by an oxide film 2, a gate oxide film 3 and a poly Si gate electrode 4 are shaped, and an n layer 5 is formed through the implantation of P ions. The layer 5 is coated with CVDSiO2 6, a side wall 6 is attached on the electrode 4 through isotropic etching and an n layer 7 is shaped through the implantation of As ions. B is implanted in depth deeper than P and As by using a resist mask. A high melting-point metal 9 is sputtered and annealed, thus forming an silicide layer 10 on the surfaces of the substrate 1 and the electrode 4. The metal 9 not reacted is removed, and the surfaces are coated with a thermal oxide film 11. A capacitance electrode 12 consisting of poly Si is annexed, thus completing a semiconductor device. Since the margin of mask alignment is unnecessitated, the semiconductor device can be fined, and not only the resistance of the surfaces of the electrode 4 and the diffusion layers 5, 7 is lowered by a metallic silicide and the working speed of the device is increased but also photo-engraving processes are decreased, thus reducing cost.

Method of producing a monolithically integrated two-transistor memory cell in accordance with MOS technology

Abstract: A method of producing a monolithically integrated two-transistor memory cell, including a silicon crystal for accommodating the memory cell, a first MOS field effect transistor having a current-carrying channel and both a control gate and a floating gate disposed between the control gate and surface of the crystal, a second MOS field effect transistor having a current-carrying channel and a control gate, an SiO 2 film supporting the gates, a doped polycrystalline silicon layer deposited on the SiO 2 film, the control gates and the floating gate being formed from the doped polycrystalline silicon layer, and an erase area for the floating gate, the improvement which includes covering a part of the silicon crystal intended for the memory cell with an SiO 2 film, forming a part of the gate oxide of the first MOS field effect transistor, forming a window through the SiO 2 film at a location intended for the erase area, re-oxidizing the exposed area of the surface of the crystal in the window and increasing the remaining areas of the SiO 2 film, depositing a first doped polycrystalline silicon layer forming a base of the floating gate, covering the polycrystalline silicon layer with another SiO 2 film, depositing a second doped polycrystalline silicon layer, and forming the control gate of the first MOS field effect transistor from the second doped polycrystalline silicon layer and producing the source and drain zone of the two MOS field effect transistors.

Storage cell for nonvolatile electrically alterable memory

Abstract: A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.

High speed and current gain insulated gate field effect transistors

Abstract: An improved insulated gate field effect transistor having a plurality of alternately positioned source and drain regions interconnected by interdigitized drain and source finger conductors making contact at a plurality of positions to a respective source or drain region. A serpentine gate conductor makes contacts to both areas of the plurality of polycrystalline gates between the plurality of source and drain regions.

Self-aligned gate method for making MESFET semiconductor

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Circuit including an mos transistor whose gate is protected from oxide rupture

Abstract: A protected MOS transistor circuit includes an input MOS transistor and a depletion mode MOS transistor having a drain-source current path connected between ground and the gate of the input MOS transistor of obviating rupture of the gate oxide of the input MOS transistor when power is off. The depletion mode MOS transistor's gate receives a control signal only when power is on which renders the depletion mode MOS transistor nonconductive when power is on. The depletion mode MOS transistor is conductive when power is off.

Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers

Abstract: A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteristics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.

Programming floating gate devices

Abstract: A memory system is provided wherein extended injection-limited programming techniques attain a substantially uniform programming behavior from an ensemble of fabricated devices or cells to provide the maximum obtainable voltage threshold shift within a minimum time period. In order to produce these desired results, a floating gate of a device is charged by applying to the control gate of the device a first voltage during a portion of this time period which produces an accelerating field in a dielectric layer disposed adjacent to the floating gate and then applying to the control gate during the remaining portion of this time period a second voltage of greater magnitude than that of the first voltage prior to or when the accumulation of charge on the floating gate causes a retarding field to be established in the dielectric layer.

An analytical expression for the threshold voltage of a small geometry MOSFET

Abstract: A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.

Polysilicon-doped-first CMOS process

Abstract: Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

HMOS-CMOS-a low-power high-performance technology

Abstract: HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-/spl mu/m channel length and 400-/spl Aring/ gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single poly technology suitable for microprocessor and static RAM applications. A 4K static RAM test vehicle is described featuring fully CMOS six-transistor memory cell, a chip size of 19600 mil/SUP 2/, 75 /spl mu/W standby power, data retention down to a V/SUB cc/ voltage of 1.5 V and a minimum chip select and address access time of 25 ns.

Measurements of deep penetration of low‐energy electrons into metal‐oxide‐semiconductor structure

Abstract: A polycrystalline Si‐SiO2‐Si metal‐oxide‐semiconductor (MOS) transistor covered with thick insulation and passivation layers of SiO2 was examined to measure the threshold voltage shifts as a function of electron energy over the range of from 5 to 18 keV. The electron‐beam fluence was varied over six orders of magnitude from 2×10−9 to 2×10−3 C/cm2. From the experimental data, the fraction of the incident electron energy deposited in the gate oxide was determined. The result shows a deep penetration of low‐energy electrons beyond the electron range.

Power static induction transistor fabrication

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. The method is characterized by use of doped polysilicon to fill the recessed gate grooves after the gate grooves have been etched and diffused. The gate grooves have depth greater than width and therefore the surface of the polysilicon layer deposit is substantially planar. The planar surface allows photolithographic techniques to be used for formation of gate contact regions and for depositing of metal gate and source electrodes.

Electrically programmable and erasable memory cell

Abstract: An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.

MOSFET Structure and process to form micrometer long source/drain spacing

Abstract: A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A well controlled sub-micrometer thickness layer is formed on these vertical sidewalls by thermal oxidation of the polycrystalline silicon surfaces. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness silicon dioxide sidewall layer portions of which extend across certain of the device regions. The sidewall layer is utilized as a mask in etching the first silicon nitride layer, the second silicon dioxide layer and the conductive layer to form the gate electrode of the field effect transistor devices in the conductive layer having the length of the sidewall coating. Ion implantation is then accomplished adjacent to the gate electrode to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.

MESFET Using a shallow junction gate structure on GaInAs

Abstract: A thin and highly doped Ga0.47 In0.53 As layer disposed on a Ga0.47 In0.53 As layer increases the barrier height and produces useful device characteristics. For example, the structure may be used as the gate electrode in an InGaAs field effect transistor.