Showing papers on "Gate oxide published in 1985"

Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs.

Abstract: This paper examines the electrical characteristics and testing considerations of gate oxide shorts Gate oxide shorts will cause increased IDD and in the majority of cases will degrade logic voltage levels and propagation delay times, but may not affect functionality Stuck-at and functional models are therefore inadequate for testing gate oxide shorts in CMOS ICs unless they are used in conjunction with IDD measurements

Hole Removal in Thin-Gate MOSFETs by Tunneling

Abstract: Fast time-resolved measurements of the response of thin-oxide MOSFETs show that radiation-induced holes are removed from the gate oxide by a tunneling process. A tunneling rate of 0.35 nm/decade from each interface is found for SiO2 at 77 K. Fast time-resolved measurements performed at room temperature are in qualitative agreement with low-temperature annealing data. Uncertainties in the room-temperature data did not allow extraction of firm and reliable values for the tunneling parameters.

Development of the self-aligned titanium silicide process for VLSI applications

Abstract: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon

Abstract: n-channel MOSFET's with channel lengths from 75 nm to 5 µm were fabricated in Si using combined X-ray and optical lithographies, and were characterized at 300, 77, and 4.2 K. Average channel electron velocities υ e were extracted according to the equation \upsilon_{e}=g_{mi}/C_{ox} , where g mi is the intrinsic transconductance and C ox is the capacitance of the gate oxide. We found that at 4.2 K the average electron velocity of a 75-nm-channel MOSFET is 1.7 × 107cm/s, which is 1.8 times higher than the inversion layer saturation velocity reported in the literature, and 1.3 times higher than the saturation velocity in bulk Si at 4.2 K. As channel length increases, the average electron velocity drops sharply below the saturation velocity in bulk Si. These experimental results strongly suggest velocity overshoot in a 75-nm-channel MOSFET.

Self-aligned recessed gate process

Abstract: An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

Abstract: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Reliability effects on MOS transistors due to hot-carrier injection

Abstract: The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-A gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

MOS dynamic ram

Abstract: A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the upper surface of each projection, a drain region of the second conductivity type formed in a bottom portion of each projection, a channel region of the first conductivity type sandwiched between the source and drain regions, a gate insulating film formed on a side wall of each projection between the source and drain regions, a gate electrode formed on the gate insulating film, a first insulating film formed on the source region, and a first electrode of the MOS capacitor formed on the first insulating film. The MOSFET is constituted by the source, drain and channel regions, the gate insulating film and the gate electrode. The MOS capacitor is constituted by the source region, the first insulating film and the first electrode, and the source region serves as the second electrode thereof. The gate electrodes serve as word lines, and the first electrodes of MOS capacitor serve as bit lines.

Conductivity-modulation type mosfet

Abstract: PURPOSE:To suppress a latch-up phenomenon and to make it possible to operate at a large current, by providing a base layer, in which a source layer is not formed, among a plurality of base layers, providing an auxiliary electrode on said base layer, and passing carriers through a p-n junction and a Schottky barrier when the carriers penetrate a source electrode. CONSTITUTION:Among a plurality of base layers 13, source layers are formed in a specified number of the base layers, and the source layers are not formed in the other base layers. High-impurity p type layers 20 are formed in the base layers 13. In the base layer 131, in which the source layer 14 is formed, a source electrode 171, which is ohmic-contacted with both the source layer 14 and the base layer 131, is formed. In the base layer 132, in which the source layer is not provided, an anxiliary electrode 172 which is ohmic-contacted with the base layer 132, is formed. The electrode 172 is connected to the source electrode 171. A drain electrode 18 is formed on the back surface of a substrate 11 by evaporation of a V-Ni-Au film. In this constitution, of a hole currents, which are injected into the p-type base layer 13, the current passing a channel part 192 flows to the auxiliary electrode 172.

Method for fabricating a self-aligned vertical IGFET

Abstract: A vertical IGFET device is formed on a substrate which includes a monocrystalline silicon portion at a surface thereof. An apertured insulated gate electrode is disposed on the substrate surface such that an area of monocrystalline silicon is exposed through the aperture. An epitaxial silicon region extends from the substrate surface within the gate electrode aperture and is appropriately doped such that a predetermined voltage applied to the insulated gate electrode forms a channel region in the epitaxial region adjacent thereto. The vertical IGFET is fabricated by a self-aligned technique, wherein the insulated gate electrode includes a first, underlying insulating layer and a second, overlying insulating layer. The second insulating layer protects the gate electrode when the first insulating layer is defined.

Investigation of the SiO2‐induced substrate current in silicon field‐effect transistors

Abstract: An experimental investigation is presented for the substrate current (holes) appearing in n‐channel field‐effect transistors having SiO2 as their gate insulator. In these experiments, the gate is biased by a high and positive voltage, causing an electron current to be injected from the device channel into the oxide. This current is accompanied by the substrate current whose origin is not clear. The experiments were performed by application of short pulses (400 μsec) to the gate. It is shown that the substrate current is too large to be explained by simple electron tunneling from the silicon valence band into the oxide. Temperature‐dependence measurements, down to 20 K, show that some of the data are not consistent with models for hole transport from the oxide into the silicon valence band. It is argued that the substrate current may be related to the energy loss experienced by hot electrons as they traverse the oxide. It is further argued that the same mechanism responsible for the substrate current may p...

Depletion mode thin film semiconductor photodetectors

Abstract: A depletion mode thin film semiconductor photodetector comprises a crystalline silicon thin film on an insulating substrate with a source region, a drain region and a thin film light sensing channel region formed therebetween. A gate oxide formed over the channel region and a gate electrode formed on the gate oxide. A p-n junction located parallel to the surface of the substrate and within the thin film functioning as a space charge separation region in the channel. The lower portion of the channel region is a p region extending to the substrate and the upper portion of the channel region is a n region extending to the gate oxide. The channel region functions as a fully depleted channel when the photodetector is operated in its OFF state providing for high dynamic range and large photocurrent operation. The depletion mode thin film semiconductor photodetector with n+ source and drain regions function as an ohmic contacts to the channel n region forming a thin film transistor. The thin film transistor photodetector has high photoconductive gain at low light intensities when the n channel region is fully pinched off by an applied gate voltage to the gate electrode which is sufficiently negative as compared to the threshold voltage of the photodetector. When the drain region is replaced by a p+ region functioning as an ohmic contact to the channel p region, a depletion mode gated diode is formed. When the channel region is extended to include a plurality of linearly spaced gate electrodes formed on the gate oxide region with an input diode formed adjacent to the first of such gate electrodes and an output diode formed adjacent to the last of such gate electrodes, the photodetector functions as a charge coupled device.

Selective anisotropic reactive ion etching process for polysilicide composite structures

Abstract: A reactive ion etching technique is disclosed for etching a gate electrode out of layers of tungsten silicide (18) and polycrystalline silicon (16) without etching the underlying layer of silicon dioxide (14) which serves as the gate dielectric and which covers the source and drain regions. The key feature of the invention, wherein the gate, which has been partially etched out of the tungsten silicide and polycrystalline silicon layers, is coated with poly tetrafluoroethylene (teflon) (30) to protect the sidewalls (24) of the gate from being excessively etched in the lateral direction while the etching continues at the bottom on either side of the gate. The process is especially suitable for formation of tungsten silicide structures since no subsequent thermal steps are required which would otherwise cause a delamination of the tungsten silicide. In addition to eliminating undercutting, the proess does not disturb the gate oxide over the source and drain areas. which would otherwise create a leaky device unsuitable for applications such as dynamic RAMs. The entire process can be carried out in a single pump down and therefore contamination levels can be minimized.

Method of making laser recrystallized silicon-on-insulator nonvolatile memory device

Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material). The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation. The recrystallized silicon is patterned into the device active area and a source and drain in alignment with the underlying gate are implanted therein.

Method of producing MOS FET type semiconductor device

Abstract: In the production of an MOS transistor or a one-MOS transistor one-capacitor memory cell, a gate electrode is made of aluminum, doped regions are formed by an ion-implantation method using the gate electrode as a mask, and the doped regions are annealed by a laser beam.

Partially relaxable composite dielectric structure

Abstract: Unique EPROM and EEPROM devices are provided with a composite dielectric layer between the control gate and the floating gate which is sufficiently thick to provide electrical and physical integrity but also has a high equivalent dielectric constant. The use of the composite dielectric layer alleviates certain problems experienced in the prior art EPROM and EEPROM devices which utilize a polycrystalline silicon floating gate and a polycrystalline silicon control gate separated by an SiO 2 dielectric layer, such as the problems of sharp silicon points resulting from polysilicon grain growth causing low dielectric breakdown strength. In contrast to the prior art, a composite dielectric layer serves as a partially relaxable dielectric between the control gate and the floating gate of an EEPROM or an EPROM. The composite dielectric layer provides high capacitance between the floating gate and the control gate without the insulative and breakdown problems encountered with prior art thin dielectric layers. Electron injection takes place through the gate oxide between the drain extension or the floating gate (EEPROM), and between the channel and the floating gate (EPROM). In another embodiment of this invention, the composite dielectric layer is also implemented between the drain extension (EEPROM) or the channel (EPROM) and the floating gate and serves as the tunnel oxide.

Application of the self‐aligned titanium silicide process to very large‐scale integrated n‐metal‐oxide‐semiconductor and complementary metal‐oxide‐semiconductor technologies

Abstract: This paper reviews recent progress towards integrating the self‐aligned titanium silicide process into VLSI NMOS and CMOS technologies, to simultaneously reduce the gate and junction sheet resistances to below 1 Ω/sq. In addition to reviewing the base line self‐aligned TiSi2 process, the key issues that must be addressed if the process is going to be successfully integrated into a VLSI process flow, without having adverse effects on device parameters, will be discussed. Such issues are how the sheet resistance can be reduced to <1 Ω/sq without bridging between the gate and source/drain regions, the effect of silicide stress on gate oxide integrity, and how both P‐ and N‐type junctions can be silicided without adversely affecting diode or transistor properties. Recent results on the hot electron hardness of silicided devices compared to unsilicided transistors will also be presented. The implementation of the self‐aligned titanium silicide process using rapid thermal processing to simultaneously fabricate transistor gates and junctions with a sheet resistance of 1 Ω/sq will also be described. Using the self‐aligned TiSi2 technology, fully functional VLSI CMOS and NMOS circuits of the 64K static random access memory class of complexity, with 1 μm gates, have been fabricated with yield that is similar to unsilicided parts.

Interface‐trap generation modeling of Fowler–Nordheim tunnel injection into ultrathin gate oxide

Abstract: Two mechanisms for interface‐trap generation during Fowler–Nordheim tunnel injection into gate oxide are confirmed by the results of experiments with changes in the interface‐trap density for positive and negative gate bias injections. One mechanism is independent of gate bias polarity during injection, the other mechanism is present only in negative gate bias injection. Agreements between the measured and calculated generation cross sections for both mechanisms indicate that: (i) The first mechanism is quantitatively explained using a broken‐bond model by taking account of electron heating due to an oxide field during passage through the oxide conduction band. (ii) The second mechanism is quantitatively explained using a heated electron impact model where electrons heated by the oxide field generate interface traps by directly breaking the interface weak bonds when electrons cross the interface between the SiO2 and the Si substrate.

Method of manufacturing a vertical MOSFET with single surface electrodes

Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

Analysis of insulated gate transistor turn-off characteristics

Abstract: A model based upon a MOSFET driving a wide-base p-n-p transistor is presented for analysis of the turn-off behavior of n-channel insulated gate transistors. This model is found to provide a very good quantitative explanation of the shape of the collector current waveform during turn-off. Verification was accomplished using insulated gate transistors (IGT's) fabricated with two voltage ratings and a variety of radiation doses. This analysis allows the separation of the channel (electron) and minority carrier (hole) current flow in the IGT for the first time.

Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate

Abstract: A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.

Reliability Effects on MOS Transistors Due to Hot-Carrier Injection

Abstract: The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-/spl Aring/ gate-oxide devices at 5.0 V operation, 2.5 /spl mu/m is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

Optimum design of n + -n - double-diffused drain MOSFET to reduce hot-carrier emission

Abstract: Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.

Process for forming a T-shaped gate structure

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess. Gate contact metal is then deposited in the opening thus formed and the nitride, photoresist and gold layers are removed, lifting off a portion of the gate metal layer thus leaving a T-shaped gate which provides a minimum length at the channel gate interface and provides a low gate resistance.

Method of manufacturing an insulated gate field effect transistor

Abstract: A method of manufacturing an insulated gate field effect transistor has first and second impurity doping processes for forming source and drain regions. In the first doping process, an impurity is lightly doped in the source and drain forming regions in self-alignment with a silicon gate pattern and a field insulating film. Next, a heat treatment is conducted so that the side surface portions of the silicon gate pattern are converted into silicon oxide films having a predetermined thickness. Thereafter, the second doping process is conducted in which an impurity is heavily doped in each part of the source and drain forming region in self-alignment with the silicon oxide films and the field insulating film. Each of source and drain region manufactured by the method has a first part of low impurity concentration adjacent to a channel region and a second part of high impurity concentration positioned between the first part and the field insulating film. The deviation of the thickness of the silicon oxide film is very small, and the length of the first part depends on that thickness. On the other hand, the length of the first part of source, drain region influences the performance of the transistor, and therefore, the method can manufacture the transistor of a stable quality.

Input protection arrangement for VLSI integrated circuit devices

Abstract: An input protection arrangement for diverting current from high voltages due to, for example electrostatic discharges into a bonding pad of an integrated circuit chip. The chip has a bonding pad connected to a conducting path and to a source or drain region of an insulated gate field effect transistor, the other region being connected to a power bus on the chip. The conducting path runs between the source and drain regions and operates as the gate terminal of the transistor. The conducting path is insulated from the surface of the chip by a field oxide insulating layer of a substantially uniform thickness to prevent rupture of the oxide between the gate and the source and drain regions in the event of high-voltages. The source and drain regions include regions of conventional doping levels having depths corresponding to the depths of the other corresponding regions on the chip, surrounded by large wells of lower doping levels. The input pad is separated from the chip substrate by an insulating oxide layer and by a doped well of the same conductivity type as the source and drain regions of the transistor to reduce the input capacitance and prevent punch through from the pad to the substrate.

Method of making MIS field effect transistor having a lightly-doped region

Abstract: An LDD MIS structure without a lightly-doped source region can be formed by the use of the conventional self-alignment technique. The structure includes in a silicon substrate a gate region, a heavily-doped drain region, a heavily-doped source region, and a lightly doped drain region. The gate region consists of a gate electrode and a side-wall spacer. The lightly-doped drain region is formed under the side-wall spacer, and in the silicon substrate.

High-voltage bipolar mode JFET with normally off characteristics

Abstract: The first realization of a power vertical JFET operated in the bipolar mode (BJFET) with normally off behavior is reported. The structure combines minority carrier injection from the gate region in the on-state, and lateral pinch-off of the channel, due to the built-in voltage, in the off-state. The realized devices show high blocking voltages, up to 900 V, with zero gate bias, and have extremely low on-resistance. Fast switching speeds with forced gate turn-off times as low as 100 ns for devices of 600-V blocking voltages have been obtained.

Method of fabricating an insulated gate type field-effect transistor

Abstract: A method of fabricating a MOS device is disclosed, in which, after formation of a gate electrode (18) and source, drain regions (22a, 22b), conductive material films (23a, 23b, 23c) are formed by selective CVD on the exposed surfaces of the gate electrode (18) and source, drain regions (22a, 22b). The conditions of the selective CVD are set such that the conductive material films (23a, 23b) formed on the source and drain regions (22a, 22b) partly overlay over the field insulating film (14) adjacent to and surrounding the source and drain regions (22a, 22b).

Method of forming vertically integrated current source

Abstract: A current source MOSFET is fabricated by forming a trench (36) in an n++ drain (source) region (32) and extending below the trench (36). A gate oxide layer (40) is disposed on the sidewalls of the trench (36) and a conductive region (38) formed in the bottom of the trench (36). A gate-to-source (gate-to-drain) contact (49) is then formed in the trench (36) and then a drain (source) contact (58) formed. The vertical gate structure defines a vertical channel region on all sides of the trench (36) to allow a wider devive to be fabricated in a smaller overall silicon area.