Showing papers on "Gate oxide published in 1986"

Single transistor electrically programmable memory device and method

Abstract: An electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate is provided having a high dielectric constant. A thin, uniform gate dielectric layer is provided which demonstrates minimal trapping. Finally, an asymmetrical source/drain junction is provided wherein the source includes a shallow portion and a deeper portion, which deeper portion defines the overlap between the source and the floating gate. In the preferred embodiment the dielectric between the control gate and the floating gate comprises tantalum pentoxide, the thin dielectric layer comprises oxynitride, and the deep diffusion portion of the source comprises phosphorous.

Self‐consistent calculation of electron and hole inversion charges at silicon–silicon dioxide interfaces

Abstract: The charge distribution at a semiconductor‐insulator interface has been calculated, both for holes and electrons, by solving Schrodinger’s and Poisson’s equations self‐consistently for particles obeying Fermi–Dirac statistics. The results have been applied to carriers in the channel of a crystalline MOSFET (metal‐oxide‐semiconductor field‐effect transistor) with the (100) axis perpendicular to the gate oxide. For weak inversion, the self‐consistent results do not deviate significantly from those obtained assuming a triangular potential well, but for strong inversion the carriers tend to move closer to the oxide. The energy and occupation levels of the subbands are only affected by a few percent on passing from weak to strong inversion, keeping the transversal interface electric field fixed. Finally the gate capacitance has been calculated and found to agree with the experimental data published elsewhere.

Electrically programmable memory device employing source side injection

Abstract: An electrically programmable and eraseable memory element using source-side hot-electron injection. A semi-conductor substrate of a first conductivity type is provided with a source region and a drain region of opposite conductivity type and a channel region of the first conductivity type extending between the source and drain regions. A control gate overlies the channel region, and a floating gate insulated from the control gate, the source and drain regions and the channel region is located either directly underneath the control gate over the channel region, partially underneath the control gate over the channel region or spaced to the source side of the control gate. A weak gate control region is provided in the device near the source so that a relatively high channel electric field for promoting hot-electron injection is created under the weak gate control region when the device is biased for programming.

Reliability and electrical properties of gate oxide shorts in CMOS ICs

Abstract: This paper examines the reliability of gate oxide shorts in CMOS ICs Gate oxide shorts cause increased quiescent IDD but may not initially affect functionality These shorts can subsequently change due to thermal and electric field stress during operation and cause functional failure Therefore, gate oxide defects can significantly degrade CMOS IC reliability 14 refs

Test Considerations for Gate Oxide Shorts in CMOS ICs

Abstract: Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-A range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC. A 100-percent stuck-at fault test set is effective only if each test vector is accompanied by an IDD measurement. This article examines the need for a fast, sensitive method of measuring IDD during each test vector and discusses problems confronting CMOS IC designers, test engineers and test instrumentation designers as they work to meet these demands.

Forming memory transistors with varying gate oxide thicknesses

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Method of making a thin film transistor with laser recrystallized source and drain

Abstract: A method of manufacturing an insulated gate field effect transistor by forming a non-single crystalline semiconductor film of a first conductivity type on an insulating substrate where the semiconductor film includes hydrogen or fluoride, forming a gate insulating film on part of the semiconductor film to be the gate region, forming a gate electrode on the insulating film, inverting the conductivity type of the part of the conductor film to be the source and grain regions by ion doping of impurity corresponding to the second conductivity type opposite to the first conductivity type with the gate electrode functioning as a mask, and then exposing the non-single-crystalline semiconductor film to illumination with the gate electrode functioning as a mask to selectively crystallize the source and drain regions.

Self-aligned split gate EPROM

Abstract: A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

A novel high-speed, 5-volt programming EPROM structure with source-side injection

Abstract: A novel source-side injection EPROM (SIEPROM) structure [1] capable of 5-volt only, high speed programming is described The cell is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control region introduced close to the source Under high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage Furthermore, the gate oxide field in this region is favorable for hot-electron injection into the floating gate As a result, a programming speed of 10 µs at a drain voltage of 5 volts has been demonstrated Also, a soft-write endurance time of 10 years with a read current larger than 100 µA per µm width can be readily achieved

Fabrication of double diffused metal oxide semiconductor transistor

Abstract: In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.

Method for producing recessed field oxide with improved sidewall characteristics

Abstract: A method for producing field oxide in a silicon substrate by forming a thin oxide layer over the surface of the substrate, forming a thin nitride layer over the thin oxide layer, forming a thick oxide over the thin nitride layer, forming a thick nitride layer over the thick oxide layer; patterning all four of the layers to espose the surface of the substrate where the field oxide is to be formed; and growing the field oxide. Preferably, before the field oxide is grown, trenches are formed into the substrate so that the upper surfaces of the field oxide are substantially planar with the upper surfaces of the substrate. The thin oxide layer minimizes bird beak formation, and eases the removal of the oxide/nitride/oxide/nitride layers. The resultant structure is both planar and bird's beak-free, and is therefore well suited to producing VLSI components having dimensions less than 0.5 microns.

MOSFET with reduced short channel effect

Abstract: An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

Abstract: A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed near V_{g} = V_{d} and a small positive gate current occurs at low V g . We argue that the dependencies of this small positive current on V g and gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.

Thin oxide fuse

Abstract: An oxide fuse, and method of forming same, formed by a thin layer of oxide dielectric between a lower electrode substrate and an upper electrode. A fuse-programming bias of approximately 15V causes Fowler-Nordheim tunneling at low temperature to damage the dielectric layer, and shorts the upper and lower electrodes together. The oxide layer is advantageously formed simultaneously with the gate oxide layer in an EEPROM.

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Abstract: Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

Abstract: A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of the G/\omega versus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.

A Pipelined 330-MHz Multiplier

Abstract: An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.

Gate turn-off thyristor with independent turn-on/off controlling transistors

Abstract: A gate turn-off thyristor has first and second MOSFETs serving as turn-on and turn-off controlling devices, respectively. A p type semiconductor layer is additionally formed in an n type substrate functioning as a first base in such a manner as to overlap a p type second base layer. The additional layer is different from the second base in impurity concentration, thereby causing the resistivity of the second base to be smaller than that of the additional layer. The first MOSFET has an n type source layer formed in the additional layer to define a surface portion of the additional layer positioned between the source layer and the first base layer as a channel region of the first MOSFET. A turn-on gate layer is provided to cover a surface region of the first base and the channel region of the first MOSFET.

Memory cell for a dense EPROM

Abstract: A memory cell has a first capacitance between a floating gate and a channel region and a second capacitance between a control gate and the floating gate. The second capacitance is less than said first capacitance, preferably much less, and there is self-alignment in two directions, resulting in a compact cell. The floating gate can have a textured surface facing the control gate. The control gate can also shift the cell operation from the enhancement mode into the depletion mode.

Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing

Abstract: MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath the source and drain regions, but not beneath the channel region. For single crystal silicon substrates, oxygen and nitrogen are the preferred ions for use in forming the buried dielectric region. The conductive gate must be sufficiently thick so as to preclude the implanted oxygen or nitrogen ions from reaching the underlying gate dielectric or the portion of and channel region of the device will be substantially free the substrate beneath the gate. This ensures that the gate and channel region of the device will be substantially free of the implant damage which otherwise occurs during formation of the buried dielectric regions. Dielectric isolation walls are conveniently provided laterally exterior to the source-drain regions. The source-drain and gate regions are self-aligned to each other. Typical oxygen implant doses to form the buried dielectric layer are 1.7.-2.2×10 18 ions/cm 2 at an energy of about 150 KeV.

Method of fabricating a self-aligned metal-semiconductor FET having an insulator spacer

Abstract: A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.

Analysis of hot-carrier-induced aging from 1/f noise in short-channel MOSFET's

Abstract: The 1/f noise of short-channel n-type MOSFET's is measured in the weak inversion regime before and after an electrical stress. The noise increase which follows the aging is shown to be due to an electrically induced generation of traps in the gate oxide rather than fast interface states. Noise experiments prove that the degradation occurs in a narrow region (less than 50 nm) near the drain. Created traps also appear to have an inhomogeneous energy profile.

A novel floating-gate method for measurement of ultra-low hole and electron gate currents in MOS transistors

Abstract: A new method for measurement of ultra-low gate currents in MOS transistors is presented. It is based on a novel coupled floating-gate transistor (CFGT) structure, which enables a clear distinction between threshold voltage shifts due to charge accumulated in the floating gate, and shifts due to device degradation. This advantage gives the new method a demonstrated sensitivity of 10-19A. In addition, with this structure it becomes possible to measure the relation between device degradation and the actual amount of charge injected to the gate. The method is demonstrated by measurements of hole and electron currents in NMOSFET's.

Nonvolatile floating gate transistor structure

Abstract: A field effect transistor includes a source region, a drain region, and a channel region formed in a semiconductor substrate and a floating gate and a control gate formed over the substrate. An opaque cover (typically aluminum) is formed over but electrically insulated from the transistor to prevent light from striking and affecting the electrical charge on the floating gate. The periphery of the opaque cover ohmically contacts the semiconductor substrate, thereby limiting the amount of light reaching the floating gate, except where the source and drain extend inwardly beyond the periphery of the opaque cover. The control gate extends over a portion of the substrate surrounding the transistor, and helps hinder light from reaching the floating gate. In addition, semiconductor material formed concurrently with the control gate extends over the source and drain regions, thereby providing additional shading.

Subchannel doping to reduce short-gate effects in field effect transistors

Abstract: One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.

Self-aligned contact process

Abstract: An improved process for self-aligned contact window formation in an integrated circuit leaves a "Stick" of etch stop on vertical sidewall surfaces to be protected. The technique includes, in the preferred embodiment, a layer of oxide over active areas and on top of the gate electrode of a transistor. The oxide is thicker on top of the gate electrode than over the active area. A silicon nitride layer acting as an etch stop is included between the oxide and interlevel dielectric such as BPSG. Contact windows may deviate from their intended position and partially overlie a poly edge such as a gate electrode or an isolation (field-shield) or field oxide edge. Two-step etching comprises first etching the BPSG down to the etch stop layer, then etching the etch stop and underlying oxide, leaving a "stick" of etch stop on the side of the layer to be protected. This process preserves for the second step of the etch the differential thickness ratio of the oxide over the gate electrodes as compared to the oxide over the active area. This process allows the simultaneous formation of self-aligned contacts to field oxide, field-shield, and gate electrode edges. It is independent of the type of gate dielectric, gate electrode material, and gate electrode sidewall processing.

Asymmetrical characteristics in LDD and minimum-overlap MOSFET's

Abstract: An asymmetrical drain, substrate, and gate current phenomenon with respect to drain-source reversal in short-channel lightly doped-drain (LDD) and minimum-overlap MOSFET has been observed. By controlled device fabrication splits, it is confirmed that these asymmetrical device characteristics are caused by the 7° off-axis drain-source implant which creates different degrees of offset between the gate edge and the source-drain junctions. The offset degrades the I-V characteristics. Substrate and gate current asymmetries are studied by analyzing the channel electrical field using two-dimensional device simulations. High-channel field at the source end is proposed to explain the second hump in the double-humped substrate current characteristic and the strong gate current injection when the devices are operated with the nonoverlap side as the source. One way to avoid the shadowing effect at ion implantation is to etch the poly-gate side wall to a small positive level angle.

Manufacture of semiconductor device

Abstract: PURPOSE:To form high melting point metal silicide with a better close adhering ability on a diffusion layer for source and drain regions of a MOS device, by forming a gate electrode, by depositing silicide, and by etching the silicide portion having silicon underlaid by using a mask of a silicon oxide film. CONSTITUTION:On the surface of a silicon substrate 11, a field oxide film 12, gate oxide film 13, polycrystalline silicon layer 14 and polycrystalline silicon gate electrode 14' are formed. After a CVD-SiO2 film is formed over the entire face, reactive ion etching forms side walls 15. Next, an N diffusion layer 16 is formed, high melting point metal silicide 17 is formed over the entire face, and then thermal oxidation forms a silicon oxide film 18. Thereafter, the portion of the silicon oxide film 18 under which there does not exist silicon is removed, only the silicon oxide film 18 on the diffusion layer 16 for the source and drain regions and on the gate electrode 14' is left, and the silicide 17 is etched using a mask of this silicon oxide film 18. Next, a PSG film 19 is evaporated, contact holes 20 are formed, and an Al film is evaporated over the entire face and is patterned to form Al wiring 21.

Self-aligned transistor method

Abstract: A method of fabrication for self-aligned gallium arsenide transistors using metal implant masks is disclosed. Preferred embodiments include use of a dummy gate (150) made of aluminum (144) on top of titanium tungsten (142) as an implant mask for source (52) and drain (54) formation with the titanium tungsten (142) undercut so that deposited silicon dioxide (62) will form a self-aligned mask for the gate deposition after the dummy gate (150) is removed.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the thin shoulder of a gate oxide film from generating on the boundary surface of a thick oxide film by forming a region of an oxide film thicker than the gate oxide film on the boundary between a diffusion layer region and a thick silicon oxide film forming an element isolation region. CONSTITUTION:A diffusion layer region 12 is formed by selectively opening a thick silicon oxide film 11; a comparatively thick silicon oxide film 10 whose thickness is larger than a gate oxide film 13 to be formed in the next stage is formed on the diffusion layer region 12: high concentration ion is selectively implanted in the comparatively thick silicon oxide film 10 except the boundary part of the thick silicon oxide film 11; selective etching is performed in order to eliminate from above the diffusion layer region 12, the high concentration ion implanted region of the silicon oxide film 10; a gate oxide film 13 is formed on the exposed surface of the diffusion layer region 12 by thermal oxidation. Thereby, the decrease of film thickness of the constricted part 18 of the gate oxide film 13 can be improved.