Showing papers on "Gate oxide published in 1987"

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

Non-volatile memory cell having Si rich silicon nitride charge trapping layer

Abstract: A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Method for fabricating MOS transistors having gates with different work functions

Abstract: A process for forming an insulated gate field effect transistor (IGFET) having a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon portion of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. The central portion of the gate is formed by conventional gate patterning whereas the end portions are formed by typical procedures for forming sidewall spacers using a conformal layer of in situ doped polycrystalline silicon (polysilicon) or other semiconductor material and an anisotropic etch.

High‐temperature depletion‐mode metal‐oxide‐semiconductor field‐effect transistors in beta‐SiC thin films

Abstract: Depletion‐mode n‐channel metal‐oxide‐semiconductor field‐effect transistors were fabricated on n‐type β‐SiC (111) thin films epitaxially grown by chemical vapor deposition on the Si (0001) face of 6H α‐SiC single crystals. The gate oxide was thermally grown on the SiC; the source and drain were doped n+ by N+ ion implantation at 823 K. Stable saturation and low subthreshold current were achieved at drain voltages exceeding 25 V. Transconductances as high as 11.9 mS/mm were achieved. Stable transistor action was observed at temperatures as high as 923 K, the highest temperature reported to date for a transistor in any material.

Heavy-Ion-Induced, Gate-Rupture in Power MOSFETs

Abstract: A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods.

Radiation Response of MOS Capacitors Containing Fluorinated Oxides

Abstract: By introducing small amounts of fluorine into the gate oxide, we have been able to significantly alter the radiation response of Metal/SiO2/Si (MOS) capacitors, and their subsequent time dependent behavior. Experimentally we have observed that compared with their control capacitors, which have no fluorine introduced into the oxide, the fluorinated samples exhibit the following major differences: (1) the densities of radiation-induced oxide charge and interface traps are drastically reduced, (2) the gate-size dependence of the radiation-induced interface traps is greatly suppressed, and (3) the overall density of the radiation-induced interface traps continues to decrease with time for many hours after irradiation before a turn-around trend is observed. Possible mechanisms involving the roles that fluorine may play in relieving the oxide strain near the SiO2/Si interface and in the post-irradiation defect-reaction chemistry are discussed.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To make a resistance of a gate electrode low while coping with shallowness of diffusion layers in source and drain electrodes by causing a silicide at a part of a gate electrode to have its thickness which is thicker than those of silicides at other electrode parts in the case of silicide film thicknesses of semiconductor device which are obtained by forming the silicides on upper parts of respective gate, source, and drain electrodes. CONSTITUTION:Element isolation regions 2 are formed on a silicon substrate 1 and a gate oxide film 3, poly Si 4, the first silicide 5a which has a high melting point and is about 2000Angstrom thick, and a silicon film 11 are formed; then, a gate electrode 101 is formed by etching. Then, N type diffusion layers 102b and 103b are formed by performing ion implantation. After forming an oxide film, side spacers 7 are formed at side faces of the gate electrode by etch-back and N type diffusion layers 102a and 103a are formed by performing ion implantation. Then, for instance, a Ti film 12 is formed on the whole surface at the thickness of about 200Angstrom and then, after treating with heat, the second silicide layers 5b and 6 are formed on the upper part of the gate electrode 101 and on the upper parts of source and drain electrodes 102 and 103 respectively at each film thickness of about 1000Angstrom . Finally, unreacted Ti is removed and the film thickness of the second silicide layer is chosen according to depths of the diffusion layers.

EPROM with increased floating gate/control gate coupling

Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

Double implanted LDD transistor self-aligned with gate

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.

EEPROM memory cell and driving circuitry

Abstract: An electrically eraseable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunneling takes place between the floating gate and the "reach through" region.

Hot-carrier-injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation

Abstract: The gate oxide region affected by injected hot electrons and/or holes along the channel is experimentally determined. The oxide region varies with bias conditions, and the device degradation rate is correlated with the change in the hot-carrier injected region. Based on these results, the following degradation mechanism is proposed: 1) The degradations in transconductance, threshold voltage, and subthreshold slope can be caused mainly by trapped electrons, but not generated interface states. 2) Enhanced degradation due to both hot-electron and hole injections is caused by electrons trapped in neutral centers produced by hot-hole injection.

A 128 K flash EEPROM using double-polysilicon technology

Abstract: An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.

Method of manufacturing a field effect transistor device having a multilayer gate electrode

Abstract: This Schottky barrier gate field effect transistor has N + -type source and drain regions formed in the surface area of a GaAs semi-insulation substrate, a channel region formed between the source and drain regions, and a gate electrode formed on this channel region. Particularly, in this Schottky barrier gate field effect transistor, the gate electrode has a first metal portion, which is preferably in Schottky contact with the channel region, and a second metal portion, which stably affixes to the first metal portion. The first and second metal portions are fixed to an insulative portion formed on the channel region.

Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation

Abstract: A new experimental method is proposed to distinguish the electron-trapping effect in the gate oxide from the interface-trap generation effect in hot-electron-induced nMOSFET degradation. In this method, by selecting the appropriate bias conditions, hot electrons and/ or hot holes are intentionally injected into the oxide region above the channel outside the drain layer, which affects MOSFET characteristics such as threshold voltage and transconductance. The negative charges of electrons trapped in the oxide during hot-electron injection are completely compensated for by the positive charges of subsequently injected and trapped holes, and the trapped electron effect in the degradation is eliminated. Using this method, the causes for hot-electron-induced transconductance degradation (Δg m /g m ) are analyzed. As the degradation increases, the trapped-electron effect decreases, and the generated interface-trap effect increases. The relationship of (Δg m /g m )_{it}, = A (Δg m /g m ) -- B is obtained, where (Δg m /g m )_{it} is g m degradation due to generated interface-traps, and A and B are fixed numbers. Furthermore φ_{it}/λ (the ratio of the critical value in hot-electron energy for interface-trap generation to the mean free path of hot electrons in Si) is experimentally obtained to be 5.7 × 106eV/cm. Using λ = 9.2 nm [1], a value of φ_{it} = 5.2 eV is derived.

EPROM device using asymmetrical transistor characteristics

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Nonplanar oxidation and reduction of oxide leakage currents at silicon corners by rounding-off oxidation

Abstract: We report that, based on the curvature radius at the convex corner of a trenched Si surface and electric field intensification, sacrificial thermal oxidation before gate oxide formation is very effective to round off the convex corner. We call it a rounding-off oxidation. From a simple one-dimensional model that considers both stress generation during Si oxidation and Stress relaxation by oxide viscous flow, it is foreseen that oxidation in a diluted oxidizing ambient and/or at a higher oxidation temperature reduces the stress in the oxide films. Experimentally, we report that the rounding-off oxidation with the above condition effectively rounds off the convex Si corner and decreases the thin gate oxide leakage currents and that the addition of a few percent of H 2 O to the dry oxygen rounding,off oxidation ambient is also effective. The relation between the sacrificial rounding-off oxidation and the time-dependent dielectric breakdown of thin gate oxides formed at the convex corner is also shown.

Method of forming metal-strapped polysilicon gate electrode for FET device

Abstract: A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H 3 PO 4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

Analysis of CMOS transistor instabilities

Abstract: A method for separation and calculation of gate oxide and surface state charges in CMOS transistors have been developed, leading to a significant improvement of the analysis of CMOS integrated circuit instabilities. In order to demonstrate the usefulness of the method, an analysis of instabilities in transistors subject to high electric field and high temperature-bias stress has been carried out. Four instability mechanisms associated with high electric field stress are observed. Successively we consider a positive gate oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps (in case of negative gate bias), electron tunneling from oxide electron traps into the oxide conduction band (in case of positive gate bias), and a surface state charge increase due to tunneling of electrons from the metal to the silicon (in case of negative gate bias) or from the silicon to the metal (in case of positive gate bias). In addition instabilities associated with high temperature-bias stress are observed: drift of mobile ions in the gate oxide, increase of positive trapped charge in the gate oxide and simultaneous increase of the surface state and negative gate oxide charges.

Method of manufacturing a thin film transistor

Abstract: A method of manufacturing a thin film transistor comprises the steps of forming a gate electrode on one surface of a transparent substrate, forming on the substrate an insulating layer and a semiconductor layer in the named order to cover the gate electrode, and depositing a positive photoresist layer on the semiconductor layer. Thereafter, the photoresist layer is exposed by irradiating from the other surface of the substrate so as to use the gate electrode as a mask. Therefore, if the positive photoresist layer is developed, the unexposed portion remains on the semiconductor layer to correspond to the gate electrode. Then, the semiconductor layer is etched using the remaining photoresist as a mask so as to form a semiconductor island on the insulating layer, and source and drain electrodes are formed on the semiconductor island.

Output buffer with improved ESD protection

Abstract: An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BVCBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground. This causes the bipolar conduction, and the associated localized J-E heating, to take place away from the surface of the semiconductor, and away from the metal or silicide layers which provide the source of material for melt filaments. A similar high threshold transistor may be provided for biasing the gate of a pull-up transistor to the power supply terminal, having the same effect in the event of an ESD pulse positive relative to the power supply terminal. The high threshold transistors may be constructed as field oxide transistors, and preferably have large channel width-to-length ratios for fast switching.

Process for manufacturing semiconductor BICMOS device

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

Manufacture of semiconductor device

Abstract: PURPOSE:To highly integrate a semiconductor device while preventing a transistor from deteriorating in its characteristics by forming an element separating insulating film of MISFET in plural steps so that at least one of the steps does not include implanting of a channel cut high density impurity CONSTITUTION:A silicon nitride film is grown on an SiO2 film 12 formed on a semiconductor substrate 11, with a mask 23 a nitride film pattern 13 is formed, and P-type impurity is implanted in high density for channel cut Then, the impurity ions 14 are implanted only out of the pattern 13 (a) Then, with the second mask 24 the second nitride film pattern 13a is formed (b) Thereafter, when a field oxide film 15 is formed by thermally oxidizing, a channel cut layer 16 is formed thereunder, but this layer does not affect the other portion of the film 15 Accordingly, the same impurity density as the substrate is obtained over the entire width W (c), the pattern 13a, the oxide film 12 are then removed, a gate oxide film is newly formed, a gate electrode 17 is formed (d), an insulating film, a wiring layer are formed to complete a transistor (e)

Scattering of silicon inversion layer electrons by metal/oxide interface roughness

Abstract: The roughness at the metal/gate oxide interface of metal‐oxide‐semiconductor field‐effect transistor (MOSFET) has been modeled. The mobility of electrons inside the channel of the MOSFET, limited by the scattering resulting from this roughness, has been calculated. The magnitude of this scattering mechanism is a strong function of the oxide thickness. For a MOSFET with very thin gate oxide (<100 A), this limiting mobility may become comparable to the total mobility, and the scattering of electrons by the remote interface roughness can no longer be ignored.

MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide

Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.

Metallization for integrated devices

Abstract: Metallization of integrated devices using ruthenium as a metallization material results in well-adhering contacts to source and drain regions as well as to gate oxide. Ruthenium is similarly suited as a diffusion barrier metallization between, e.g., silicon and aluminum and as an interconnection metallization material. And, as a diffusion barrier material, ruthenium dioxide may be used.

Controlled Atomic Layer Doping and ALD MOSFET Fabrication in Si

Abstract: Controlled atomic layer doping (ALD) in Si is obtained, combining the adsorption and desorption behaviours of Sb in Si molecular beam epitaxy and solid phase epitaxy. SIMS and CV measurements confirm the sharp doping profile. It is shown by Hall measurements that the carrier concentration varies from 9×1011 to 8×1013 cm-2 and the mobility from 250 to 60 cm2V-1s-1 when the Sb concentration is changed from 0.0015 to 1 monolayer. The first ALD-MOSFET, with a gate length of 8 µm and a gate oxide thickness of 100 nm, is made using the ALD layer as the conducting channel, and has a transconductance of 7 mS/mm.

Characteristics of the Si‐SiO2 interface states in thin (70–230 Å) oxide structures

Abstract: Important characteristics of the Si‐SiO2 interface states, such as the interface state density distributions and the electron and the hole capture cross section versus energy profiles, were investigated in unannealed metal/silicon dioxide/silicon (MOS) structures with the gate oxide thickness in the range of 70–230 A, using the optical MOS admittance technique. The experimentally obtained interface state density distribution, in case of p‐Si/SiO2/Al structures, exhibited two peaked profiles, one near the valence‐band edge Ev and the other near the conduction‐band edge Ec, overlying a concave background. The state density at the peak was observed to undergo a maximum, preceded by a minimum, as the gate oxide thickness tox was increased. The peak energy versus tox and the capture cross section versus tox profiles also indicated strong features.

Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide

Abstract: The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.

50-&#197; gate-Oxide MOSFET's at 77 K

Abstract: While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin gate-oxide (52-A) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-induced degradation may not be the limiting factor in choosing the power-supply voltage and special drain structures may be necessary for very thin gate MOSFET's even at 77 K. However, mobility reduction at high V G is more severe both at lower temperatures and for thinner oxides. Electron mobility appears to be oxide-thickness-dependent at 77 K. The dependence of the electron mobility on the normal field is so strong that it results in unusual I-V characteristics such as negative transconductance at 77 K for an oxide field above 3 MV/cm. The I--V characteristics have been modeled with a mobility dependence on V GS of the form µn ∞ (1 + η(V GS - V t /T ox )2+ (E/E c ))-1for 52-A devices.

Method of fabricating field-effect transistor utilizing improved gate sidewall spacers

Abstract: Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36) The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions No significant gate dielectric encroachment occurs Also, the spacers achieve a profile that substantially avoids electrical shorts