Showing papers on "Gate oxide published in 1988"

Modeling and characterization of gate oxide reliability

Abstract: A technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented. Using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. This modeling procedure is applicable to both wafer-level and long-term reliability tests. Process improvements including defect gettering and alternative dielectrics such as chemical-vapor-deposited oxides are evaluated in the format of defect density as a function of effective oxide thinning. >

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Abstract: A novel transistor with compact structure has been developed for MOS devices This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge >

Floating-gate transistor with a non-linear intergate dielectric

Abstract: A non-volatile memory cell having a floating-gate transistor is disclosed, which has a ferroelectric material for the dielectric between the floating gate electrode and the control gate electrode. The ferroelectric material provides for non-linear capacitance characteristics with voltage, and is polarizable into two states by the application of voltage across the capacitor plates of sufficient magnitude. The memory cell is read by applying a voltage to the control gate electrode which will sufficiently be capacitively coupled to the floating gate electrode to turn on the transistor when the ferroelectric material is in the programmed state, but which will not be sufficiently coupled in the erased state to turn the transistor on. The ferroelectric material may be incorporated directly above the floating gate transistor electrode, or may be formed remotely from the transistor between two metal layers, the lower of which is connected to the floating gate electrode.

Time dependence of interface trap formation in MOSFETs following pulsed irradiation

Abstract: The time dependence of interference trap (N/sub it/) formation in MOSFETs was studied as a function of gate oxide thickness, oxide growth type, substrate orientation, temperature, and gate bias. Two different N/sub it/ formation mechanisms are observed. Most (typically 90%) of the formation, called the late process, occurs slowly at long times (1-10000 s) after the radiation pulse. From a variety of experimental data, it is concluded that the rate of the late process is limited by drift of a radiation-induced positive ion, probably H/sup +/, through the gate oxide to the Si-SiO/sub 2/ interface where the N/sub it/ are formed. A relatively fast, or early, process is responsible for a small percentage of the total N/sub it/ formation. The time constant for this process appears to be consistent with hole drift through the oxide. >

Thin film transistor array

Abstract: A thin film transistor array in which a plurality of thin film transistors arranged in the shape of an array on a substrate each transistor includes a gate electrode, a first insulating layer, a semiconducting layer, a second insulating layer, a source electrode and a drain electrode stacked sequentially one on another such that the first insulating layer and the second insulating layer are interposed at an overlap portion between a gate bus bar for connecting the gate electrodes in common and a source bus bar for connecting the source electrodes in common.

Semiconductor integrated circuit device

Abstract: PURPOSE:To make it easy to keep the lapping margin of wiring, and increase reliability of the wiring, by making the diameter of a connection hole of an insulating film large in the wiring direction, and small in the crossing direction with the wiring. CONSTITUTION:On an n layer 5 on a p substrate which is separated in insulated regions 2 and 3, a gate oxide film 4 and an interlayer insulating film 7 are stacked, and a resist mask 8 is formed to make a connection hole 9. A new mask 10 has an rectangular aperture pattern which is long in the direction of wiring arrangement and has a width equal to the hole 9 in the perpendicular direction. By applying the mask 10, an anisotropic dry etching is performed, and the thickness of the insulating film 7 is made on half. The mask 10 is removed and an Al wiring 11 is formed. In the perpendicular direction to extension of the wiring 11, the wall surface is vertical, and defects of the buried wiring hardly generate. On the other hand, the connection hole 9 is in the form of a step in the direction of extension, so that the wiring 11 and the n layer 5 or a gate electrode 6 are excellently connected.

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

Abstract: Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film. >

Multigigahertz CMOS dual-modulus prescaler IC

Abstract: A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 AA have been used. The best prescalar fabricated with 175-AA gate oxide functions at 2.06 GHz with 25-m W power consumption (L/sub eff/=0.5 mu m; V/sub dd/=3.5 V). Preliminary results for prescalars fabricated with 100-AA gate oxide show that 4.2-GHz operation is possible (L/sub eff/=0.4 mu m; V/sub dd/=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW. >

Method for programming a floating gate memory device

Abstract: A method of programming a floating gate transistor permits the use of a charge pump to provide drain programming current. The programming drain current is typically held below about 1 μA. This programming drain current can be provided by a conventional charge pump. In the first embodiment, the drain current can be limited by connecting a resistor between the source and ground. In a second embodiment, the drain current is limited by limiting the transistor control gate voltage. In a third embodiment, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. In these embodiments the erase gate voltage may be raised to enhance programming efficiency.

Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors

Abstract: Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4*10/sup 16/ cm/sup -3/, the drain saturation current in ultrathin SOI transistors is predicted to be approximately 40% larger than that of bulk structures. An increase of approximately 30% is seen in measurements made on devices in 1000-A SOI films. >

Structure for protecting thin dielectrics during processing

Abstract: A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.

Method of manufacturing a DMOS

Abstract: A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

Thin oxide sidewall insulators for silicon-over-insulator transistors

Abstract: A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer

Abstract: A method of fabricating a SALICIDED self aligned metal oxide semiconductor device using a disposable silicon nitride spacer, metal silicide and a single implant step for the source, drain and gate regions is disclosed. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. Fourth, a cobalt layer is deposited on the wafer and processed to form cobalt silicide, after which the cobalt that did not come in contact with the silicon or the polysilicon gate region is removed. Fifth, the nitride layer on the walls of the gate region is removed. Sixth, a single ion implant step is used to form the N-channel Transistors of the device. Seventh, a single ion implant step is used to form the P-channel transistor of the device.

Semiconductor device with silicon oxynitride over refractory metal gate electrode in LDD structure

Abstract: A semiconductor device uses a high melting point metal such as tungsten, molybdenum, etc. at its gate electrode and wirings for higher operation speed. In particular, the top and the side of the gate electrode and wirings are covered by a layer of silicon oxynitride whereby the gate electrode and the wiring are protected from oxidation and deterioration which may be cause by heat treatment in an oxidative atmosphere and ion implantation.

EPROM fabrication process

Abstract: An EPROM fabrication process using CMOS N-well technology with a two polysilicon floating gate stack and a double layer of conductive lines providing a large process tolerance latitudes, a small reliable memory cell and high density. Channel stops and field oxide are formed by implanting boron ions, followed by a high temperature drive-in and oxidation cycle with a 1000-2500 Å thick nitride mask covering device areas. The floating gate stack is formed by forming a first gate oxide layer depositing a first polysilicon layer having a thickness of 2000-2600 Å, removing these layers from non-memory cell areas, growing a uniformly thick second oxide layer at 1100°-1200° C. over both the substrate and first polysilicon layer, depositing a second polysilicon gate layer and selectively etching away the layers to form first the device gates and second memory all gate from the second polysilicon layer, and then the floating gate from the first polysilicon layer using the second gate as a self-aligning mask. Metal coverage in the double layer of conductive lines is improved by rounding corners of glass and intermetal layers by means of glass reflow and planarization and wet/dry etching of the intermetal layer.

Manufacture of thin film transistor matrix

Abstract: PURPOSE: To prevent the generation of a short-circuit between a gate bus line and a drain bus line by a method wherein, after the gate bus line and a gate electrode are formed on an insulative substrate 1, side etchings are further performed in a degree that an insulating film on the gate electrode is removed. CONSTITUTION: An NiCr film 11 is formed on a glass substrate (a transparent insulative substrate) 1 and moreover, an SiNX film 12 is formed as an insulating film. Then, unnecessary parts are selectively removed. Subsequently, side etchings are performed in a degree that the film 12 is removed from the upper part of a gate electrode to form an interlayer insulating film 8 on the film 11 constituting a gate bus line GB. Then, an SiNX film (a gate insulating film) 2, an operating semiconductor layer 3 and an insulating film 4 are formed. Subsequently, a contact layer 6 and a metal film 7 for drain and source electrode use are formed and source and drain electrodes S and D and a drain bus line DB are formed. In an obtained TFT, as the SiNX film 8, which is used as the interlayer insulating film, is interposed between the gate and drain bus lines GB and DB in addition to the film 2, the risk of the generation of a short-circuit between the bus lines is significantly reduced. COPYRIGHT: (C)1990,JPO&Japio

LDD transistor process having doping sensitive endpoint etching

Abstract: An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

EEPROM using a merged source and control gate

Abstract: A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor. In the above structure, the poly-Si layer acts as the floating gate over the channel of the sense transistor. Since the poly-Si floating gate is both capacitively coupled to the source of the sense transistor and to the source of the write transistor, no separate control gate or control gate electrode is needed (the source of the sense transistor acts as the control gate). The structure, inter alia, enables a higher coupling ratio during erasing, thus allowing faster erase times by coupling a higher voltage onto the poly-Si floating gate.

Reference potential generating circuit

Abstract: A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.

Dual LDD submicron CMOS process for making low and high voltage transistors with common gate

Abstract: The disclosure relates to a CMOS flow process for formation of high and low voltage transistors simultaneously in a single semiconductor chip. The low and high voltage transistors share the same gate oxide thickness and the same polysilicon gate level. This is accomplished without any additional masking steps and through the use of a separate lightly doped drain for the high voltage N-channel devices. The sources of the high voltage N-channel devices are fabricated using the more heavily concentrated LDD implant normally used for the low voltage transistors. This minimizes the source resistance of the high voltage transistor which results in higher performance through improved saturated transconductance. From a high voltage capability point of view, the flow permits the realization of a single level polysilicon single gate oxide thickness low/high voltage CMOS process.

Gate controllable lightly doped drain mosfet devices

Abstract: An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.

The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs

Abstract: The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., Delta V/sub T/ and Delta I/sub D/) have become intolerably degraded. In the extreme cases of stressing at V/sub G/ approximately=V/sub T/ with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism. >

Semiconductor device having a two-layer gate structure

Abstract: A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drain regions via a gate insulating film and serving as a floating gate electrode, a two-layer insulating layer formed on the first conductive layer and consisting of a silicon oxynitride film and a silicon oxide film, and a second conductive layer formed on the two-layer insulating layer and serving as a control gate electrode. In the semiconductor device of this structure, the silicon oxynitride film traps fewer electrons, and electrons are infrequently trapped at the time of data erasing, so that data-erasing characteristics can be improved. Further, since fewer electrons are trapped, unlike the prior art insulating layer utilizing a silicon nitride film, there is no need for providing any silicon oxide film on each side, and with the two-layer structure consisting of the silicon oxynitride film and a silicon oxide film it is possible to obtain sufficient insulation and film thickness reduction.

Electrically erasable and electrically programmable read only memory

Abstract: A semiconductor memory device having a MOS transistor with a floating gate capable of storing data. The MOS transistor has an erase gate which overlaps part of the floating gate with an insulating film interposed therebetween. Upon application of a high voltage on the erase gate, the field emission is caused between the floating gate and the erase gate and the charge stored on the floating gate is removed.

Individual oxide traps as probes into submicron devices

Abstract: In field‐effect transistors with gate areas less than 0.5 μm2 the effect of a single electron trapped in the gate oxide on the device resistance is easily observable. In about 10% of these devices a single thermally activated two‐state trap produces most of the low‐frequency resistance fluctuations in a wide bandwidth near room temperature. Detailed information about this single oxide interface trap can be extracted from the temperature and bias dependence of the trapping kinetics. In this work we extend this technique to locating the trap between the source and drain. With this information these traps become unique local 5–50 A probes into submicron devices to study the local surface potential and the sensitivity to localized trapped charges under different bias conditions.

Defect formation in SiO2/Si(100) by metal diffusion and reaction

Abstract: The decomposition of SiO2 films on Si(100) during ultrahigh vacuum anneal is found to be strongly enhanced by monolayer amounts of impurities deposited on the SiO2 surface. s‐ and p‐band elements initiate decomposition via formation of volatile suboxides by surface reaction, whereas most transition metals decompose the oxide via laterally inhomogeneous growth of voids in the oxide. Transition metals need to diffuse to the SiO2/Si interface to enhance oxide decomposition via formation of volatile SiO. It is inferred that transition metal particles should be efficient in creating electrical defects in gate oxide layers.

Semiconductor device having an improved thin film transistor

Abstract: There is disclosed a semiconductor device provided with an improved thin film transistor which is formed on a semiconductor substrate via an insulating layer and which comprises a gate electrode, a semiconductor film, a source region and a drain region formed in the semiconductor film, a junction between the drain region and a channel region being not overlapped with the gate electrode.

Manufacture of semiconductor device

Abstract: PURPOSE:To stabilize a transistor in characteristics by a method wherein a first gate electrode is formed, a second N.type impurity layer is formed by diffusion on the entirety or a prescribed region of a semiconductor substrate, and, in a second gate channel region, unnecessary portions of the second N-type impurity layer and the semiconductor substrate are subjected to etching. CONSTITUTION:A first N-type diffusion layer 3 is formed on a silicon substrate 1. Next, a first gate oxide film 4 is formed and, thereon, a first polycrystalline silicon 5 is formed. The first polycrystalline silicon 5 and the first gate oxide film 4 are patterned, which is accomplished according to the geometry of a second resist mask 6. An N-type impurity is diffused into the primary surface of the silicon substrate 1, and then a second N-type diffusion layer 7 is formed. A process follows wherein a third resist mask 8 is formed and the silicon substrate 1 is etched through the second and third resist masks 6 and 8. In this process, etching is so accomplished as to remove only the portions of the first N-type diffusion layer 3 and the second N-type diffusion layer 7 located not under the second and third resist masks 6 and 8. This method realizes a transistor with its characteristics stabilized.