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Showing papers on "Gate oxide published in 1989"


Proceedings ArticleDOI
03 Dec 1989
TL;DR: A fully depleted lean channel transistor (DELTA) with a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported in this paper.
Abstract: A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported In the deep submicron region, selective oxidation is useful for achieving SOI isolation It provides a high-quality crystal and a Si-SiO/sub 2/ interface as good as those of conventional bulk single-crystal devices Using experiments and simulation, it was shown that the gate structure of DELTA has effective channel controllability and its vertical ultrathin ( >

266 citations


Journal ArticleDOI
TL;DR: In this article, the effect of postoxide-growth fluorine incorporation in gate dielectrics is reported, and it is explained by a model wherein fluorine bonds to silicon, and the displaced oxygen grows the additional oxide.
Abstract: The effect of post-oxide-growth fluorine incorporation in gate dielectrics is reported. Fluorine was introduced through ion implantation into polysilicon and diffused into the gate oxide, as indicated by SIMS measurements. No great decrease in the breakdown field was observed, although a decrease in charge-to-breakdown was seen. Interface characteristics also improved with medium to high doses of fluoride. High doses were found to grow additional oxide. NMOS FETs showed increased immunity to hot-electron-induced stress. These results are explained by a model wherein fluorine bonds to silicon, and the displaced oxygen grows the additional oxide. >

262 citations


Patent
28 Aug 1989
TL;DR: In this article, a process for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions is described.
Abstract: A process is disclosed for the formation of an LDD structure in an MOS transistor having a reduced mask count and providing high integrity source/drain junctions. In accordance with one embodiment of the invention an MOS transistor is formed having a gate dielectric overlying an active region of the substrate. A transistor gate is formed in a central portion of the active region and an oxidation layer is formed over the active region and the transistor gate. A lightly-doped source/drain region is formed which is self aligned to the transistor gate. A conformal layer of an oxygen reactive material is formed overlying the transistor gate and the active region. The oxygen reactive material is anisotropically etched in a oxygen plasma reactive ion etch to form a sidewall spacer on the edge the transistor gate. The oxygen reactive ion etch does not penetrate the oxidation layer overlying the active region. A heavily-doped source/drain region is formed which is self aligned to the edge of the sidewall spacer. The sidewall spacer is then removed completing the LDD structure.

196 citations


Patent
Masahiro Shirasaki1
30 Jun 1989
TL;DR: A metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body, a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate, except for the part of the channel regions in contact as mentioned in this paper.
Abstract: A metal-insulator-semiconductor transistor comprises an insulator layer, a semiconductor body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the semiconductor body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer. The channel region has a width substantially smaller than twice the maximum extension of the depletion region formed in the channel region.

158 citations


Patent
28 Aug 1989
TL;DR: In this article, a high power MOSFET is disclosed in which a plurality of hexagonal base regions formed in the surface of a chip receive respective hexagonal annular source regions.
Abstract: A high power MOSFET is disclosed in which a plurality of hexagonal base regions formed in the surface of a chip receive respective hexagonal annular source regions. The base regions are relatively shallow and of relatively low conductivity material. A central portion of each of the base regions reaches the upper surface of the wafer and contacts a sheet source electrode which also contacts the source regions. The central regions of the base elements which contact the source electrode are of higher conductivity than the main base portion for a distance extending just below the depth of the source regions. The base regions are formed by ion implantation through a gate oxide which is exposed by a window in an overlying polysilicon layer. After ion implantation and driving of the base regions, an annular source region is diffused into each base, employing the same polysilicon window as an outer mask. A central oxide dot may be left in the center of each of the open windows so that the oxide is thicker at the central regions and remains in place during the diffusion of the source regions.

135 citations


Patent
02 Nov 1989
TL;DR: In this paper, a self-aligned, opposed gate-source transistor was constructed by resonant dielectric lithography, where the gate side of the thin film is irradiated by collimated ultraviolet light to expose a negative resist on the source side with a resolution of less than a wavelength.
Abstract: Methods of fabricating electrical contacts on both sides of a thin membrane to form a millimeter wave, self-aligned, opposed gate-source transistor are disclosed. The transistor structure has a subhalf-micron gate, dual-drains placed symmetrically around both sides of the gate, and a source approximately half the length of the gate. The source is directly opposite, and centered under, the gate on the opposite surface of a semiconductor thin film. The gate electrode is fabricated on the first surface of the thin film using conventional single surface lithography, and is used as a conformed mask for the source lithography, thereby self-aligning the source to the gate. The source is formed by resonant dielectric lithography, wherein the gate side of the thin film is irradiated by collimated ultraviolet light to expose a negative resist on the source side with a resolution of less than a wavelength. Lateral diffraction effects affect the relative dimension of the source with respect to the gate. The electron-beam lithographic process utilizes electron scattering in the thin film for the same purpose. This new untraviolet lithography process avoids the need to handle the thin film until after source metallization has been completed.

102 citations


Patent
29 Nov 1989
TL;DR: In this article, a conductivity modulated MOSFET with a gate electrode formed on a gate insulating film which is formed on channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer.
Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

90 citations


Patent
17 Jan 1989
TL;DR: In this article, a CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers is presented, where the cell pitch is equal to the first and second metallisation pitches.
Abstract: A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to a grid, and referencing the polysilicon layer to a half grid. Further refinements include the use of channel regions between parallel and adjacent chains of complementary transistors, wherein the width of the channel is equal to three times the pitch of the cell. In another form, a base set of the gate array includes diffused resistors in the channel regions suitable for matching discretionary interconnection.

80 citations


Patent
19 Jul 1989
TL;DR: In this paper, a method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an ammorphous silicon layer and a protective layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape.
Abstract: A method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an amorphous silicon layer and a protective insulating layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape, in such a manner as to not cover the connecting terminal region of the gate wiring. A protective insulating layer is patterned into a predetermined shape. After passing through a predetermined production process to produce an amorphous silicon thin film transistor array, at least a gate wiring and a source wiring are provided. The step of patterning the protective insulating layer comprises covering the connecting terminals of the gate wiring and the exposed region of the glass substrate with a photoresist.

80 citations


Journal ArticleDOI
Chih-Yuan Lu1, J.M. Sung1, H.C. Kirsch1, Steven James Hillenius2, T.E. Smith2, L. Manchanda2 
TL;DR: In this paper, the C-V characteristics of arsenic-doped polysilicon have been investigated with quasistatic and high-frequency capacitors and conductance measurements of various capacitors.
Abstract: The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.

80 citations


Patent
Seiichi Iwamatsu1
02 Jun 1989
TL;DR: A trench gate MOS FET has one of the following features: a drain diffusion layer and/or a source diffusion layer having a two-layer structure consisting of a high concentration layer and a low concentration layer.
Abstract: A trench gate MOS FET having one of the following features: a drain diffusion layer and/or a source diffusion layer having a two-layer structure consisting of a high concentration layer and a low concentration layer; at least a drain diffusion layer having a low concentration layer adjacent to the semiconductor surface of a trench gate and a high concentration layer adjacent to the low concentration layer; a gate oxide film formed to have a greater thickness at the overlapping portion of the diffusion layer and the gate electrode than at the other portions thereof; two trench gates provided on the semiconductor surface so as to control the conductivity of a channel region between the trench gates; or a trench isolation region provided on the semiconductor substrate in contact with the trench gate.

Patent
16 Jun 1989
TL;DR: In this paper, a vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistors are formed in and along one of the sidewalls of the structure.
Abstract: A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.

Journal ArticleDOI
TL;DR: In this article, the impact of metal contamination on the quality of gate oxides was investigated using a pinhole detector and the failure mechanism was found to be related to the formation of Cu-rich precipitates at the SiO2/Si interface.
Abstract: To study the impact of metal contamination on the quality of gate oxides, (100) silicon wafers were intentionally contaminated with copper from the backside. The in‐diffusion of copper and/or oxidation were performed in a rapid thermal annealing system. Gate oxide areas with low breakdown fields of about 2–3 MV/cm were located in a pinhole detector and correlate very well with the contaminated areas revealed by Secco defect etching. Using various analytical tools the failure mechanism was found to be related to the formation of Cu‐rich precipitates at the SiO2/Si interface. Depending on the in‐diffusion temperature (and hence on the supersaturation of Cu in Si), two different mechanisms were observed: At high supersaturation (1200 °C/30 s) Cu‐rich silicide particles can bend, crack, and finally penetrate the oxide layer. At lower in‐diffusion temperatures (900 °C/60 s) lens‐shaped Cu silicides form at the SiO2/Si interface and reduce the oxide thickness.

Proceedings ArticleDOI
01 Dec 1989
TL;DR: In this paper, a novel MOSFET structure which has a small occupied area for 64-Mb DRAMs (dynamic RAMs) is proposed, where the source-drain regions are raised by using a selective silicon growth technique.
Abstract: A novel MOSFET structure which has a small occupied area for 64-Mb DRAMs (dynamic RAMs) is proposed. The source-drain regions are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over the gate and the field, the contact area can overlap the gate and the field. Moreover, the shallow source-drain junction of the raised source-drain structure realizes the reduction of the gate length and the isolation spacing. As a result, the MOSFET can minimize the total occupied area. It has been verified that this MOSFET has the potential to realize high-density LSIs such as 64-Mb DRAMs. >

Patent
17 May 1989
TL;DR: In this article, a dopant-opaque layer of polysilicon (32) is deposited on gate oxide (26) on a silicon substrate (18, 20) to serve as a pattern definer.
Abstract: A dopant-opaque layer of polysilicon (32) is deposited on gate oxide (26) on a silicon substrate (18, 20) to serve as a pattern definer. It controls successive P and N doping steps used to form operative DMOSFET regions within the substrate, a trench (63) in the silicon surface, and conductive structures (28, 30) atop the substrate. A source conductive layer 28 is deposited in the trench to electrically contact source region (24) as a gate conductive layer (30) is deposited atop the gate oxide 26. The trench sidewall (64, 65) is profile tailored using a novel O₂-SF₆ plasma etch technique. An oxide sidewall spacer (62) is formed on the sides of the pattern definer (32) and gate oxide (26), before depositing the conductive material (28, 32). A planarizing layer (72) is used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Journal ArticleDOI
TL;DR: A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models that take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of M OS transistors.
Abstract: A unified approach is proposed for modeling gate oxide shorts in MOS transistors using lumped-element models. These models take into account the possible structure of gate oxide short and the resulting changes that affect the I-V characteristics of MOS transistors. They can be used with the circuit simulator to predict the performance degradation of the VLSI circuit with gate oxide shorts. Demonstrated examples of models show close agreement with the experimental data. >

Patent
18 Oct 1989
TL;DR: In this paper, a double gate static induction thyristor was proposed, where gate electrodes are formed on the first and second gate regions, and main electrodes are created on the main electrodes, so that portions of the semiconductor regions surrounded by the gate regions formed a current path between the gate electrodes.
Abstract: A double gate static induction thyristor comprises a semiconductor substrate, a first gate region formed at a first principal surface of the substrate, and a first semiconductor region of a first conduction type formed on the same first principal surface. A second gate region is formed at a second principal surface of the substrate, and a second semiconductor region of a second conduction type is formed on the same second principal surface. Gate electrodes are formed on the first and second gate regions, and main electrodes are formed on the first and second semiconductor regions, so that portions of the semiconductor regions surrounded by the gate regions form a current path between the main electrodes. Further, impurity is deeply diffused in portions of the first and second gate regions formed with the gate electrodes.

Patent
17 Apr 1989
TL;DR: In this paper, a gate electrode movable and deformable by pressure is formed above the gate insulation film through the hollow chamber, and an auxiliary gate electrode is provided on the boundary plane between the gate insulating film and hollow chamber.
Abstract: A pressure sensor of the field-effect type includes a transistor having a gate insulation film above which a hollow chamber is provided, a gate electrode movable and deformable by pressure is formed above the gate insulation film through the hollow chamber, and an auxiliary gate electrode is provided on the boundary plane between the gate insulation film and hollow chamber, whereby the value of pressure can be detected by the drain-current variation of the transistor

Patent
Tiao-Yuan Huang1
24 Nov 1989
TL;DR: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer is presented in this article.
Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.

Journal ArticleDOI
TL;DR: In this paper, the effect of fluorine incorporation in the gate oxide on the NMOSFET hot-electron immunity is examined, and the results of Auger measurements are correlated with a fluorine deficient layer near the interface.
Abstract: The effect of fluorine incorporation in the gate oxide on the NMOSFET hot-electron immunity is examined. Fluorine is implanted in the polysilicon gate and diffused into the gate oxide. The hot-electron immunity of NMOSFETs is shown to increase with increasing fluorine doses. Measurement of device lifetime against substrate current shows that higher doses of fluorine lead to a change in the immunity to interface trap generation. Based on the results of Auger measurements, this has been correlated with a fluorine deficient layer near the interface. >

Proceedings ArticleDOI
G. Miller1, J. Sack1
26 Jun 1989
TL;DR: In this paper, an IGBT (insulated-gate bipolar transistor) is presented which is based on bulk silicon material without a buffer layer and it is shown that such a device with a breakdown voltage of 1400 V and a short-circuit capability of 1200 V at 20 V gate voltage has on-state and switching losses that are not higher-maybe even lower-than those of a buffer-layer device if its backside p-emitter efficiency is kept low enough.
Abstract: An IGBT (insulated-gate bipolar transistor) is presented which is based on bulk silicon material without a buffer layer. In contrast to other devices the carrier lifetime was kept as high as possible. It is shown that such a device with a breakdown voltage of 1400 V and a short-circuit capability of 1200 V at 20 V gate voltage has on-state and switching losses that are not higher-maybe even lower- than those of a buffer layer device if its backside p-emitter efficiency is kept low enough. >

Patent
Chi Chang1
15 Sep 1989
TL;DR: In this article, an electrically programmable floating gate transistor with a low doping concentration, less than 5x10¹¸cm³, and a thickness of less than 1000A was proposed to provide self-limiting erase characteristic.
Abstract: An electrically programmable floating gate transistor useful as a one transistor flash EPROM cell (90) includes a multi-thickness dielectric (110) provided on a substrate (100). The multi-thickness dielectric limits tunnelling from a floating gate (114) provided on the multi-­thickness dielectric to a drain (104) during programming and allowing tunnelling from the floating gate (114) to the source (108) during erasing. The floating gate (114) has a low doping concentration, less than 5x10¹⁸cm⁻³, and a thickness of less than 1000A to provide a self-limiting erase characteristic.

Patent
26 Dec 1989
TL;DR: In this paper, a dual-layer cap of silicon oxide and silicon nitride is used to protect a refractory metal silicide during high-temperature processing using a dual layer cap.
Abstract: A method for protecting a refractory metal silicide during high-temperature processing using a dual-layer cap of silicon oxide and silicon nitride. The problem of a silicon nitride protective layer detaching itself from an underlying refractory metal silicide layer during high-temperature processing, thus allowing tungsten atoms within the layer to oxidize, is solved by laying down a silicon oxide layer beneath the silicon nitride layer. The oxide layer acts as a mechanical stress relief layer between the refractory metal silicide and the silicon nitride layer, preventing the lifting of the nitride layer during high-temperature processing steps.

Patent
22 May 1989
TL;DR: In this article, a gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide.
Abstract: A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes. The selectively deposited polycrystalline silicon extends upwardly from the source and drain regions onto the field oxide. The sidewall spacers provide physical and electrical isolation between the gate electrode and the adjacent source and drain electrodes.

Patent
M.J. Schindler1
04 Dec 1989
TL;DR: The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer as discussed by the authors.
Abstract: An advanced MESFET switching structure which includes an interdigitated source region and an interdigitated drain region, also includes a gate electrode region disposed between adjacent portions of the interdigitated source and drain regions having a series gate electrode in Schottky barrier contact therewith. The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer. Moreover, the topography permits smaller MESFET structures and thus higher integration of circuits employing the advanced MESFET switch structure. The smaller transistors will also have lower parasitic reactances. In a preferred embodiment, all interconnections for drain, gate, and source electrodes are disposed on the active layer portion of the transistor providing an even smaller transistor structure.

Patent
Mizutani Yoshihisa1
27 Feb 1989
TL;DR: In this paper, a memory cell is selected by dropping the bias voltage on the second diffusion layer and the potential on the first diffusion layer is kept unchanged to constantly maintain the initially-applied bias voltage even when the memory cell was selected, so that the first-layer is permitted to be coupled to the common wiring line together with the corresponding first diffusion layers of the other memory cells.
Abstract: A memory cell structure for a non-volatile semiconductor memory has a semiconductor substrate and first and second diffusion layers having a conductivity type opposite to that of the substrate, formed on the substrate and serve as a source and a drain. The second diffusion layer is coupled through a contact hole to a conductive layer that serves as a bit line. The functions of the first and second diffusion layers as the source and drain are reversed between data write and read modes. A floating gate and a control gate are insulatively provided on the substrate in parallel to each other. In either the data write mode or data read mode, the first and second diffusion layer are applied with a bias voltage while the control gate is initially applied with a ground voltage. A memory cell is selected by dropping the bias voltage on the second diffusion layer. The potential on the first diffusion layer is kept unchanged to constantly maintain the initially-applied bias voltage even when the memory cell is selected, so that the first diffusion layer is permitted to be coupled to the common wiring line together with the corresponding first diffusion layers of the other memory cells.

Patent
15 Mar 1989
TL;DR: In this article, a double-injection transistor structure with an MOS gate is utilized as a guided-wave electro-optic phase modulator at infrared wavelengths in a silicon-on-insulator (SOI) waveguide.
Abstract: A double-injection transistor structure with an MOS gate is utilized as a guided-wave electro-optic phase modulator at infrared wavelengths in a silicon-on-insulator (SOI) waveguide. Cathode, gate and anode regions are integrated in the waveguide, longitudinally. The effective phase modulation is given by the voltage-variable overlap of the guided-mode optical field with carrier-induced local changes in the silicon refractive index. An electron-hole plasma is injected under the gate by cathode and anode. Using depletion-layer widening, the plasma channel width and mode overlap are controlled very rapidly by one or two low-power gate electrodes.

Patent
Ogura Seiki1, Nivo Rovedo1
07 Nov 1989
TL;DR: In this article, a method for fabricating a Bi-CMOS device including both vertical PNP and NPN components is presented, which includes forming the reach-through N+ subcollector to the bipolar device without extra processing steps, combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a selfaligned, removable oxide mask prior to field isolation.
Abstract: A method for fabricating a Bi-CMOS device including both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks. The device incorporates similar structural features between the bi-polar and FET devices. The NPN and PFET can share the same well and a P+ diffusion (the P+ extrinsic base is the same as the P+ source). Also, the PNP and NFET can share the same well and an N+ diffusion.

Patent
07 Dec 1989
TL;DR: In this article, a three element memory cell, including the memory device and two FETs, is described, which operates from a constant, non-switched supply voltage and two-level control voltages.
Abstract: A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.

Patent
03 Oct 1989
TL;DR: In this paper, a source/drain contact region is formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon.
Abstract: A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.