Showing papers on "Gate oxide published in 1991"

A neuron-silicon junction: a Retzius cell of the leech on an insulated-gate field-effect transistor.

Abstract: An identified neuron of the leech, a Retzius cell, has been attached to the open gate of a p-channel field-effect transistor. Action potentials, spontaneous or stimulated, modulate directly the source-drain current in silicon. The electronic signals match the shape of the action potential. The average voltage on the gate was up to 25 percent of the intracellular voltage change. Occasionally weak signals that resemble the first derivative of the action potential were observed. The junctions can be described by a model that includes capacitive coupling of the plasma membrane and the gate oxide and that accounts for variable resistance of the seal.

Applications of Quantum Semiconductor Structures

Abstract: This chapter discusses the applications of quantum semiconductor structures A new heterostructure type of FET has been developed that includes the two-dimensional electron gas field effect transistor also called high electron mobility transistor, modulation doped field effect transistor, or selectively doped heterojunction transistor depending on manufacturer It has features in common with both MESFETs and metal-oxide-silicon field effect transistors The structure is based on the heterojunction between AlGaAs and GaAs Its essential structure consists of a semi-insulating substrate on which is first grown a buffer layer of nonintentionally doped GaAs and on top of this is grown a thin layer of Al x Ga 1− x As, part of which is rather heavily n-type doped The gate metal forms a Schottky barrier to the AlGaAs and by making the ternary layer thin enough, the gate can completely deplete the AlGaAs layer of electrons Then the density of electrons on the GaAs side of the heterojunction is controlled by the voltage applied to the gate, so that the current between the source and the drain contacts can be controlled by the gate voltage

Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Abstract: An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portion of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.

A MOS gate drive with resonant transitions

Abstract: A resonant gate-drive circuit for MOS power transistors is described. The gate drive provides quasi-square-wave gate-to-source voltage with low impedance between gate and source terminals in both on and off states. Input capacitance of the power MOS transistor is charged and discharged in a resonant circuit so that switching losses in the gate drive are eliminated. This is particularly important in high-frequency and low-power applications. A detailed loss analysis yields closed-form solutions for gate-drive and total switch losses. These results are used to select the MOS power transistor with minimum losses, and to compare the gate drive with resonant transitions against the conventional gate drive. >

Process for preparing a polycrystalline semiconductor thin film transistor

Abstract: A process for preparing a polycrystalline semiconductor thin film transistor wherein a non-singlecrystalline semiconductor formed on a transparent insulating substrate is annealed by laser beams, such process comprising forming a gate insulation layer and a gate electrode on the non-singlecrystalline semiconductor; implanting impurity ions into a source-drain region of the semiconductor wherein the gate electrode is used as a mask, and irradiating laser beams from the rear surface side of the transparent insulating substrate to thereby polycrystallize the non-singlecrystalline semiconductor under the gate electrode or improve the crystallinity of the semiconductor without causing the non-singlecrystalline semiconductor in a completely molten state.

Self-aligning contact and interconnect structure

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Abstract: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

Power MOSFET transistor circuit with active clamp

Abstract: A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the opposite conductivity type extending into the substrate from the first surface; and a source region of the one conductivity type extending into the substrate from the first surface within each of the body regions, the interface of each of the source regions with its respective body region at the first surface being spaced from the interface of its respective body region and the drain region at the first surface to form a channel region therebetween. A gate electrode overlies and is insulated from the first surface and extends across the channel regions. A conductive electrode extends over and is insulated from the gate electrode, and contacts at least a portion of the source regions. A current limiting circuit is coupled between the conductive electrode and the gate electrode and a voltage limiting circuit is coupled between the drain electrode and the gate electrode.

Current vs. logic testing of gate oxide short, floating gate and bridging failures in cmos

Abstract: Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.

Fermi threshold silicon-on-insulator field effect transistor

Abstract: A silicon-on-insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

Conductivity modulated MOSFET

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Process for fabricating a silicon on insulator field effect transistor

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current

Abstract: A silicon carbide field-effect transistor is provided which includes a semiconductor substrate, a channel formation layer of silicon carbide formed above the substrate, source and drain regions provided in contact with the channel formation layer, a gate insulator disposed between the source and drain regions, and a gate electrode formed on the gate insulator, wherein a first contact between the channel formation layer and the drain region exhibits different electric characteristics from those of a second contact between the channel formation layer and the source region. Also provided is a method for producing such a silicon carbide field-effect transistor.

Manufacture of semiconductor device

Abstract: PURPOSE:To suppress the deterioration of a gate oxide film by a method wherein a gate is formed on a substrate and thereafter, silicon is implanted in drain regions for N layer formation and a polysilicon region and after this, an impurity for drain formation is implanted and the impurities are electrically activated in such a way as to perform a heat treatment. CONSTITUTION:Boron is channel-doped to a silicon substrate 1 and thereafter, a gate oxide film 2 is formed. Then, a polysilicon film 3 is deposited and the films 2 and 3 located at regions other than a gate are removed by etching. After this, a resist 5 is deposited on regions other than regions, where are used as drain regions 6 for N layer formation, and the gate region and silicon is implanted in the regions 6 for N layer formation and the polysilicon region using this resist 5 as a mask. Then, the resist 5 is removed, an oxide film 4 is formed on the gate and arsenic is ion- implanted using this film 4 as a mask to form N layer. After this, after an oxide film is deposited, sidewalls 9 are formed by anisotropic etching and arsenic is implanted to form N layers 8. After this, each impurity enters the position of the lattice of a silicon crystal by a heat treatment and is electrically activated. Thereby, gentle concentration distributions can be respectively obtained from a channel region toward the drain layers.

Semiconductor device having an MOS transistor with overlapped and elevated source and drain

Abstract: Source and drain electrodes which are overlapped and elevated with respect to an inverse-T gate electrode provide low lateral electric field, low source-drain series resistance, and uniform source and drain doping profiles while maintaining a compact layout. In one form of the invention, a semiconductor device (10) has source and drain electrodes (40) which are elevated and overlap shelf portions (21) of an inverse-T gate electrode (19). LDD regions (28) are formed in a substrate (12) and partially underlie the gate electrode. Facets (41) of the selectively deposited source and drain electrodes overlie the shelf portions of the gate electrode, thereby creating uniform doping profiles of heavily doped regions (42).

N-channel clamp for ESD protection in self-aligned silicided CMOS process

Abstract: An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

Low‐rate plasma oxidation of Si in a dilute oxygen/helium plasma for low‐temperature gate quality Si/SiO2 interfaces

Abstract: Low‐rate plasma oxidation of Si, involving a small oxygen concentration in a low‐power He plasma at low processing temperatures (∼350 °C), is shown capable of producing excellent interface properties, good uniformity, and low defect density. As an interfacial layer for plasma‐enhanced chemical vapor deposited (PECVD) SiO2 films, the plasma oxide is key to achieving high quality composite (plasma oxide/PECVD) oxide structures, which essentially match the electrical quality of thermal oxides. Such low‐temperature oxide films are suitable for critical device applications, such as the gate oxide in metal‐oxide‐semiconductor devices and the base passivation layer in advanced bipolar devices.

Split-gate field effect transistor

Abstract: A field effect transistor having a gate voltage swing in the transistor channel varying as a function of position between the drain and the source. The gate voltage swing in the transistor channel may be made to vary as a function of position by making the threshold voltage a function of position. Alternatively, a split-gate device may be used by applying a voltage between the gates. In both cases, the electric field near the source is raised to accelerate the electrons thereby decreasing electron transit time.

Trench isolation method having a double polysilicon gate formed on mesas

Abstract: A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.

Mosfet with substrate source contact

Abstract: A MOSFET (90,105,170) having a back-side source contact (94,169) and top-side gate (104,166) and drain contacts (98,168) is provided by a structure comprising superposed N⁺ (97,136), N- (96,132),P- (95,128), N⁺ (92,120) regions arranged between top (99,137) and bottom (93,121) surfaces of the semiconductor die (90,105,170). In a preferred implementation, two trenches (100,108) (148,149) are etched from the top surface (99,137) to the P- (95,128), N⁺ (92,120) interface. A buried P- (95,128), N⁺ (92,120) short (110,162) is provided in one trench (108,148) and a gate dielectric (102,160) and gate electrode (104,166) are provided over the sidewall P- (95,128) region exposed in the other trench (100,149). This creates a vertical MOSFET (170) in which the N⁺ substrate (92,120) forms the source region shorted to the P- body region (95,128) in which the channel (106) is created by the gate (104,166). Superior performance is obtained in RF grounded-source circuit applications.

Dynamic effects in SOI MOSFET's

Abstract: The use of SOI (silicon-on-insulator) and conventional bulk MOSFETs by circuit designers is similar in a wide range of functions for logic purposes. Differences may appear when asynchronous design is used, due to floating body effects. The consequences of direct coupling between drain and source of a MOSFET in the OFF-state are discussed, and the characterization of this effect for various SOI technologies is presented. Two mechanisms are proposed to explain the results: a capacitive coupling between drain and floating body, which corresponds to a drain to source coupling when the floating body follows the source potential; and a dynamic bipolar effect in which the base current is constituted by the gate oxide charge in accumulated mode. This effect leads to a parasitic drain to source discharge, which can result in an upset in a SRAM memory cell or in a dynamic latch. It is found that a careful design must be done if functions like dynamic or static latch are needed. >

Manufacture of semiconductor device

Abstract: PURPOSE:To enhance the reliability by a method wherein an oxide film is provided on the side of a wiring conductive film provided on the upper part of field oxide films and a gate electrode while an insulating film is provided on the sides of opening parts for contact. CONSTITUTION:Field oxide films 2 are selectively provided on a P type Si substrate 1; a gate oxide film 3 is provided on the surface of the films 2; and B ions are implanted in the substrate 1 using the films 2 as masks. Next, a silicon oxide film 5 is deposited on the surface to selectively form a gate electrode 4 while P ions are implanted using the electrode 4 and the films 2 as masks to form N-type diffused regions 6. Another silicon oxide film 7 is deposited on the surface; arsenic ions are implanted in the substrate 1 leaving the film 7 only on the sidewall part of the electrode 4; N type diffused region 8 connecting to the region 6 are formed and then the other silicon oxide film 9 is deposited on the whole surface. Finally, a polycrystal Si film 10 is deposited on the whole surface and after reflowing process to flatten the surface, the films 10, 12 in the opening part 13 formed by processing a photoresist film 12 coated on the whole surface are removed and then the other silicon oxide film 4 is deposited to form electrode wirings 15. Through these procedures, the insulation between the wirings 15 and the conductive films as well as the reliability can be enhanced.

Nonvolatile semiconductor device

Abstract: In a nonvolatile semiconductor memory device with a two-layer gate structure, an interlayer insulating film is formed on a floating gate electrode of, e.g., polycrystalline silicon. The interlayer insulating film has a four-layer structure in which a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film are laminated in this order on the floating gate electrode, or a two-layer structure in which a first silicon nitride film and a first silicon oxide film are laminated in this order on the floating gate electrode. With the above structure, the threshold voltage of the semiconductor device is stabilized even after data-erase operation. Since, moreover, the first silicon oxide film can be formed by oxidizing the first silicon nitride film, then the quality of the first silicon oxide film can be enhanced, and accordingly the charge retaining properties of the device can be increased.

Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor

Abstract: A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.

A method for the fabrication of low leakage polysilicon thin film transistors

Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520°-570° C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650° C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650° C. and hydrogenating the resistive transistor with a hydrogen plasma.

Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate

Abstract: A single transistor electrically programmable and erasable memory cell (10) has a substrate (12) of a semiconductor material of a first-conductivity type (18). Within the substrate are defined source (16), drain (14), regions with a channel region (18) therebetween. A first insulating layer (20) is disposed over the subtract (12) and over the source (16) channel (18) and drain (14) regions. An electrically conductive, re-crystallized floating gate (22) is disposed over the first-insulating layer (20) and extends over a portion of the channel region (18) and over a portion of the drain region (14) to maximize capacitive coupling therewith. A second insulating layer (25) has a top wall portion (24) over the floating gate (22) and a side wall portion (26) immediately adjacent to the floating gate (22) and has a thickness which permits the Flowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate (29) has two electrically connected sections: a first section (30) is over the first insulating layer (20) and is immediately adjacent to the side-wall portion (26) of the second insulating layer (25). The first section (30) extends over a portion of the channel region (18) and over the source region (16). A second section (28) is disposed over the top wall portion (24) of the second insulating layer (25) to minimize capacitive coupling with the floating gate (22).

High-power-density GaAs MISFETs with a low-temperature-grown epitaxial layer as the insulator

Abstract: A GaAs layer grown by molecular beam epitaxy at 200 degrees C is used as the gate insulator for GaAs MISFETs. The gate reverse breakdown and forward turn-on voltages, are improved substantially by using the high-resistivity GaAs layer between the gate metal and the conducting channel. It is shown that a reverse bias of 42 V or forward bias of 9,3 V is needed to reach a gate current of 1 mA/mm of gate width. A MISFET having a gate of 1.5*600 mu m delivers an output power of 940 mW (1.57-W/mm power density) with 4.4-dB gain and 27.3% power added efficiency at 1.1 GHz. This is the highest power density reported for GaAs-based FETs. >

Gate oxide damage from polysilicon etching

Abstract: Damage to thin gate oxides from etching of polysilicon gates was studied using gate oxide breakdown histograms and time‐dependent dielectric breakdown measurements. The effect of various polysilicon etch parameters was investigated in a radio frequency (rf) triode etcher. Increasing rf power caused a substantial increase in damage. Reducing bias at constant power also resulted in an increase in damage, indicating that ion energy is not the only cause of damage. Area, isolation edge, and source/drain edge contributions to gate oxide defect densities were calculated as a function of rf power during polysilicon etch. As rf power was increased, the area contribution increased the most, indicating that gate oxide damage from polysilicon etching is not an edge phenomenon but a surface phenomenon. The effect of gate oxide thickness was investigated. Damage increased significantly as gate oxide thickness was reduced. Finally, the rf triode etcher was compared with a microwave electron cyclotron resonance (ECR) et...

Magnetron etching of polysilicon: Electrical damage

Abstract: We report comparison of etch damage between reactive ion and magnetron plasma etch environments and propose a qualitative model. Gate oxide damage is controlled by both plasma current and voltage and under some conditions can be worse for magnetron etching, especially in the case of very thin gate oxide. Moderate magnetron voltages (<50 V) may still be high enough (given the increased plasma density) to charge polysilicon gates causing degradation. Further reduction of voltage (and hence current) through modification of geometry and chemistry can reduce this damage to gate oxide and the gate edge diode for magnetron etching, producing results superior to reactive ion etching.