Showing papers on "Gate oxide published in 1992"

A single transistor non-volatile electrically alterable semiconductor memory device

Abstract: A single transistor electrically programmable and erasable memory cell (10) is disclosed. The single transistor has a source (14), a drain (16) with a channel region (18) therebetween, defined on a substrate. A first insulating layer (20) is over the source, channel and drain regions. A floating gate (22) is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer (25) has a top wall which is over the floating gate, and a sidewall which is adjacent thereto. A control gate has a first portion (24) which is over the first insulating layer and immediately adjacent to the sidewall of the second insulating layer. The control gate has a second portion (26) which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.

Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode

Abstract: An IGFET has differential crystallinity in offset regions near the source-channel and drain-channel boundaries. In one embodiment, an offset region with crystallinity different from that of an adjacent region is provided between the channel and at least one of the source and drain regions. An oxide film may be provided to cover the surface of the gate electrode, formed by anodizing the surface of the gate electrode, and this layer may be used as a mask when forming the crystallinity offset regions.

Thin-oxide damage from gate charging during plasma processing

Abstract: The plasma-induced charge damage to small gate gate MOS capacitors is investigated by using 'antenna' structures. After an O/sub 2/ plasma step the interface state density increases with increasing antenna area and varies by two orders of magnitude. A hole trapping-induced breakdown mechanism during plasma charging is supported by experimental evidence which includes annealing and polarity effects for charge to breakdown and tunneling currents. In addition, oxide susceptibility is shown to depend on oxide growth conditions and is predictable by negative bias-temperature aging. >

Semiconductor device with oxide layer

Abstract: An insulated gate field effect semiconductor device comprising a substrate having provided thereon a thin-film structured insulated gate field effect semiconductor device, said device being characterized by that it comprises a metal gate electrode and at least the side thereof is coated with an oxide of the metal. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact holes for the extracting contacts of the source and drain regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate. Furthermore, the present invention provides a method for forming insulated gate field effect semiconductor devices using less masks.

Proposal for Surface Tunnel Transistors

Abstract: A new three-terminal tunnel device, the surface tunnel transistor (STT), is proposed and its operation is demonstrated using GaAs/AlGaAs. STT consists of n+/i/p+ diode structure with an insulated gate in the i-region, which is similar to a MOSFET. However, the source and drain are oppositely doped. The most important feature of this device is that the drain must be so highly degenerated that a tunnel junction is formed with a two-dimensional (2D) electron channel under the gate. The tunneling current from source to drain is controlled by the gate bias through the concentration of accumulated 2D electrons under the gate. GaAs STTs with i-Al0.6Ga0.4As as a gate insulator are fabricated using MBE regrowth techniques on a mesa structure. This device exhibits transistor characteristics at 77 K and at room temperature, which confirms the new operation principle of STTs.

Method for forming a MOS transistor and structure thereof

Abstract: A method for forming a MOS transistor having LDD structure by a simple and a few number of processes and a structure thereof are described. In accordance with the present invention, a low concentration of an impurity region can be formed in a semiconductor film part between an end of gate electrode and source or drain, by forming an ordinary gate insulating film extending beyond the gate electrode in the direction along the source and drain, in place of a spacer in the side of gate electrode which has been required for a preparation of conventional TFT having LDD structure, and further by forming a thinner insulating film than the gate insulating film in the side thereof, and by utilizing the thickness difference between the gate insulating film part excepting the gate electrode and the thin insulating film in the side thereof.

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

Abstract: A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10/sup 14//cm/sup 2/, the LDD and fully overlapped LDD devices exhibit similar GIDL current. >

Method for forming a transistor having silicided regions

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Recognition of D defects in silicon single crystals by preferential etching and effect on gate oxide integrity

Abstract: A method for revealing point defects in silicon single crystals has been investigated. D or A defects could be revealed by a preferential etching technique using Secco's etchant. Wedge-shaped flow patterns and etch pits were recognised in the D and A regions, respectively. The flow patterns were so characteristic that the D region could be distinguished very easily.

Insulated gate field effect transistor

Abstract: A power MISFET using an oxide semiconductor is provided. A drain electrode and a gate electrode having a trapezoidal cross section are formed with a semiconductor layer provided therebetween, a semiconductor layer is formed on a side surface of the gate electrode, and a source electrode is in contact with the semiconductor layer at a portion which overlaps with the top of the gate electrode. Between the drain electrode and the source electrode of such a power MISFET, a power source of 500 V or more and a load are connected in series, and a control signal is input to the gate electrode. Other structures and operating methods are also disclosed.

Trench isolation using gated sidewalls

Abstract: The invention is directed to improving trench isolation between active devices by using gated sidewalls. In a first embodiment, trenches are etched into the substrate and a thin oxide film is formed to passivate the trench sidewalls and serve as a sidewall gate oxide. The oxide is removed from the bottom of the trench while leaving the sidewall oxide intact. A thin poly layer is formed into the trench so that the thin poly does not completely fill the trench, yet the thin poly film will overlie the oxide sidewalls and make contact to the exposed substrate at the bottom of the trench. The trench is then completely filled with a conformal oxide that is planarized. The planarized oxide is etched during thermal oxide etch and a sacrificial oxide is grown. Following threshold adjust implants, the sacrificial oxide is removed and the final gate sidewall oxide is formed. In a second embodiment, the process steps vary by leaving the thin oxide film at the bottom of the trench and then forming a thin poly film over the thin film oxide. The steps then continue as in the first embodiment and the thin poly in the trench is later tied to the substrate at points on the die external from the trench.

Acoustic-phonon runaway and impact ionization by hot electrons in silicon dioxide.

Abstract: We present model calculations for high-field electron transport in silicon dioxide based on recently measured energy-dependent electron-phonon scattering rates and impact ionization rates. We find a hot-electron runaway phenomenon in ${\mathrm{SiO}}_{2}$, ``acoustic-phonon runaway.'' This phenomenon occurs at electric fields exceeding 7 MV/cm, when acoustic-phonon scattering can no longer stabilize the hot electrons. A fraction of the electrons are accelerated in the electric field to energies high enough to generate electron-hole pairs by impact ionization. Simulated hole currents due to high-field impact ionization in ${\mathrm{SiO}}_{2}$ gate oxides with thicknesses greater than 200 A\r{} agree well with measured substrate hole currents in n-channel field-effect transistors. This suggests that these currents are due to holes generated by hot-electron impacts in the gate oxide.

Furnace nitridation of thermal SiO/sub 2/ in pure N/sub 2/O ambient for ULSI MOS applications

Abstract: Furnace nitridation of thermal SiO/sub 2/ in pure N/sub 2/O ambient for MOS gate dielectric application is presented. N/sub 2/O-nitrided thermal SiO/sub 2/ shows much tighter distribution in time-dependent dielectric breakdown (TDDB) characteristics than thermal oxide. MOSFETs with gate dielectric prepared by this method show improved initial performance and enhanced device reliability compared to those with thermal gate oxide. These improvements are attributed to the incorporation of a small amount of nitrogen ( approximately 1.5 at.%) at the Si-SiO/sub 2/ interface without introducing H-related species during N/sub 2/O nitridation. >

Electrical analysis and modeling of floating-gate fault

Abstract: It is demonstrated that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate oxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. An electrical study of the floating gate fault is presented. A theoretical model taking into account the influence of the transistor's environment is proposed. Analytical expressions for the equivalent gate-to-source voltage are derived, and the FGTs electrical operation mode is analyzed. This model is validated by SPICE simulations and by actual device measurements. The problem of testing for FGTs is discussed. >

Electrically erasable and programmable semiconductor memory device with trench memory transistor and manufacturing method of the same

Abstract: A p-type silicon substrate 1 is provided with a trench 11. A second gate oxide film 4 is formed on a bottom wall 11a of the trench. The trench has a side wall 11b on which a first gate oxide film 9 is formed. A thickness of the second gate oxide film 4 is smaller than that of the first gate oxide film 9. A floating gate electrode 5 is formed on the second and first gate oxide films 4 and 9. At the vicinities of the opposite ends of the floating gate electrode 5, there are formed an n + -drain diffusion region 2 and n + -source diffusion region 3. A control gate electrode 7 is formed over the floating gate electrode 5 with an layer insulating film 6 interposed therebetween. In an electrically programmable and erasable semiconductor memory device (EEPROM) of a flash type, a writing efficiency is improved, a reliability is improved with respect to quality control, and dimensions of memory transistors are reduced.

Conductivity-modulation metal oxide field effect transistor with single gate structure

Abstract: There is disclosed a single-gate type conductivity-modulation field effect transistor having a semiconductive substrate, a base layer, and a source layer formed in the base layer A source electrode is provided on a surface of the substrate, for electrically shorting the base layer with the source layer A drain layer is provided in the substrate surface A drain electrode is formed on the substrate surface to be in contact with the drain layer A gate electrode is insulatively provided above the substrate surface, for covering a certain surface portion of the base layer which is positioned between the substrate and the source layer to define a channel region below the gate electrode A lightly doped semiconductor diffusion layer is formed in the substrate surface so as to overlap said base layer and said drain layer The diffusion layer having an impurity density which is varied continuously through the thickness of the diffusion layer

Hole mobility enhancement in MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructure inversion layers

Abstract: Effective hole mobility enhancements of 50% at room temperature and over 100% at 90 K, compared to all-Si controlled devices, are demonstrated by placing a buried epitaxial Ge/sub x/Si/sub 1-x/ layer 7.5 to 10.0 nm beneath the gate oxide of a PMOS transistor. Mobility degradation caused by misfit dislocations in the inversion region is seen in structures with GeSi/sub 1-x/ layers that exceed the equilibrium critical thickness. >

Process for improving sheet resistance of an integrated circuit device gate

Abstract: A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above the gate. The portion of the passivating layer above the gate is removed with little or no effect on the insulating layer or gate. A trench above one or both junctions (source or drain) is formed by removing insulation using the passivating layer as an etch stop, then removing a portion of the passivating layer above the junction with little or no effect on the junction or any isolation region present. The gate may be further silicided, and the opening above the gate and the trench above the junction may each be planarly filled with a low sheet resistance conductive material, forming contacts. The contact above the junction may be borderless.

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

Abstract: A high-performance 0.25- mu m-channel CMOS technology is designed and characterized. The technology utilizes n/sup +/ polysilicon gates on nFETs and p/sup +/ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, C/sub w/=0.2 pF) delay per stage of 280 ps at W/sub eff//L/sub eff/=15 mu m/0.25 mu m, which is a 1.7* improvement over 0.5- mu m CMOS technology. At a channel length of 0.18 mu m, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed. >

Semiconductor memory cell and memory array with inversion layer

Abstract: A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.

Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications

Abstract: When applying a high voltage to the floating gate of a split-gate transistor, enhanced hot-electron injection is observed that can be used for 5-V compatible EPROM or flash EEPROM device operation. The current collected on the gate is equal to the total electron injection current. Charge-pumping measurements and device simulations are used to analyze the electron injection and to determine its exact position in the transistor channel. Gate currents only show a weak dependence on both transistor channel lengths. The width of the spacer between both transistor gate has, however, been determined to be an important injection parameter. >

Composite dielectric for a semiconductor device and method of fabrication

Abstract: A high-quality, highly reliable, composite dielectric layer for a semiconductor device. The composite dielectric layer is formed by nitriding a silicon surface, forming an oxide layer on the nitrided silicon surface, and then annealing the nitrided-silicon surface and the oxide in an oxygen ambient.

High density power device fabrication process

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).

Semiconductor device and method of manufacturing the same

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Method of manufacturing SOI semiconductor element

Abstract: According to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.

Silicon carbide MOSFET having self-aligned gate structure

Abstract: A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity α6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer, epitaxially grown on the substrate layer, includes a steep-walled groove etched through the n+ SiC layer and partially into the p SiC layer. The groove is lined with a thin layer of silicon dioxide which extends onto the n+ type conductivity layer. A filling of gate metal over the layer of silicon dioxide is contained entirely in the groove. The silicon dioxide layer includes a first window extending to the filling of gate metal in the groove, and second and third windows extending to the n+ type conductivity layer on either side of the groove, respectively. A gate contact extends through the first window to the filling of gate metal in the groove while drain and source contacts extend through the second and third window, respectively, to make contact with the n+ type conductivity layer in drain and source regions on either side of the groove.

Semiconductor device having a thin-film transistor and process

Abstract: A semiconductor device having a thin-film transistor (22) and a process for making the device. The semiconductor device includes a substrate (11) having a principal surface. A gate electrode (29) overlies the principal surface and a gate dielectric layer (23) overlies the gate electrode (29). A conductive channel interface layer (25) overlies the upper surface of the gate electrode (29) and is spaced apart from the gate electrode (29) by the gate dielectric layer (23). A conductive thin-film layer (57) overlies the gate electrode (29) and forms a metallurgical contact to the channel interface layer (25). Remaining portions of the thin-film overlie the principal surface and form source and drain regions (63, 65) of the thin-film transistor (22). The thin-film source and drain regions (63, 65) are formed by placing a diffusion barrier cap (60) over the channel portion (61) of the thin-film layer (57) and introducing conductivity determining dopant into the thin-film layer (57). A silicide is formed in the thin-film source and drain regions (63, 65) by the depositing a refractory metal layer over the thin-film layer (57) and the diffusion barrier cap (60) and annealing the thin-film layer (57).

Low on resistance field effect transistor

Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).

A physical model for MOSFET output resistance

Abstract: The output resistance (R/sub out/) most important device parameters for analog applications. However, it has been difficult to model R/sub out/ correctly. In this paper, we present a physical and accurate output resistance model that can be applied to both long-channel and submicrometer MOSFETs. Major short channel effects and hot-carrier effect, such as channel-length modulation (CLM), drain-induced-barrier-lowering (DIBL) and substrate current induced output resistance reduction, are all included in this model, and it is scalable with respect to different channel length L, gate oxide thickness T/sub ox/ and power supply V/sub dd/. This model can be incorporated into existing MOSFET's model without introducing discontinuity. >

Self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device

Abstract: A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.