Showing papers on "Gate oxide published in 1993"

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Threshold voltage model for deep-submicrometer MOSFETs

Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

Metal semiconductor field effect transistor based on single crystal GaN

Abstract: In this letter we report the fabrication and characterization of a metal semiconductor field effect transistor (MESFET) based on single crystal GaN. The GaN layer was deposited over sapphire substrate using low pressure metalorganic chemical vapor deposition. MESFET devices were fabricated on isolated mesas using TiAu for the source and drain ohmic contacts and silver for the gate Schottky. For devices with a gate length of 4 μm (channel opening, i.e., source to drain separation of 10 μm), a transconductance of 23 mS/mm was obtained at −1 V gate bias. Complete pinch‐off was observed for a gate potential of −12 V.

New Phenomena of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna

Abstract: The effect of antenna shape on charge damage has been examined using electron cyclotron resonance (ECR) plasma metal etching and test devices with an 8-nm-thick gate oxide. A dense-line antenna causes capacitor breakdown and the positive shift of the transistor's threshold voltage (Vt), while a sparse-line antenna does not. This positive Vt shift corresponds to a positive charge-up of the dense line, and is not dependent on overetching. Such damage is hardly observed when the antenna's top surface is exposed to the plasma, indicating that the plasma is uniform in terms of conventional charge damage. These new phenomena can be explained by a new mechanism consisting of electron shading with photoresist patterns. This shading leads to less neutralization of the ion charge impinging onto the transitory metal which remains between the antenna lines because of the microloading effect, and thus the excess positive charge causes the damage.

Thin-film transistor and a liquid crystal matrix display device using thin-film transistors of this type

Abstract: A thin-film transistor comprises a gate electrode formed on a glass substrate, a gate insulating film formed essentially over an entire surface of the substrate to cover the gate electrode, a non-single-crystal silicon semiconductor film placed on the gate insulating film to cover the gate electrode; and a drain electrode and a source electrode spaced a specified distance apart on the semiconductor film and electrically connected to the semiconductor film so as to form the channel region of the transistor. The gate electrode is made of titanium-containing aluminum.

Post‐irradiation cracking of H2 and formation of interface states in irradiated metal‐oxide‐semiconductor field‐effect transistors

Abstract: Molecular hydrogen is alternately introduced into and removed from the gate oxide of irradiated metal‐oxide‐semiconductor field‐effect transistors at room temperature by changing the ambient between forming gas (10/90% H2/N2) and nitrogen. Using charge pumping, it is observed that H2 causes a simultaneous buildup of interface states and decrease of trapped positive charge. The results are explained by a reaction sequence in which H2 is cracked to form mobile H+, which under positive bias drifts to the Si/SiO2 interface, and reacts to produce a dangling‐bond defect. The rate limiting step over most of the time domain studied is the cracking process. Two types of cracking sites are modeled by molecular orbital calculations: oxygen vacancies (E’ centers) and broken bond hole traps (BBHTs). Initial‐ and final‐state energies, as well as the activation energies, are calculated. The calculations indicate that the latter is the more likely H2 cracking site. The combined experimental and theoretical results sugges...

Semiconductor memory cell

Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

Thin film transistor array having single light shield layer over transistors and gate and drain lines

Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate The gate lines intersect with the drain lines TFTs are formed at the intersections of the gate lines and the drain lines An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images

Vertical power MOSFET structure having reduced cell area

Abstract: In a vertical power field effect transistor, a side surface of a gate electrode is covered with a side oxide film, and a groove is formed in self-alignment with the side oxide film to extend from a surface area of a silicon substrate between a pair of adjacent gate electrodes, to reach a base region. A tungsten film is filled into the groove thus formed, and a source electrode-is formed in contact with the tungsten film within the groove.

Field-effect transistor with perovskite oxide channel

Abstract: A field-effect transistor (FET) is described having a source; a drain; a channel formed between the source and the drain; and a gate electrode. The channel is composed of a film layer of oxide having the perovskite structure comprised of: (1) at least one metal selected from the group consisting of the metal elements in Group IV through Group XI of the Periodic Table of Elements and Bi; and (2) at least one metal selected from the group consisting of alkali metals, alkaline earth metals and rare earth metals. The layer has a film thickness of not larger than 1000 Å and the electrical resistivity not less than 2 million centimeters. The channel of the oxide film layer is provided with a metal oxide insulator layer formed directly or through another metal oxide insulator layer and a gate electrode in electrical contact therewith. It is possible to make memories using this FET. In addition, it also becomes possible to reduce the size of devices using the FET of the invention.

Self-aligned power MOSFET device with recessed gate and source

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80). Layers (86, 90) have a lateral thickness (88) established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers. Source conductor (94) in the second trench contacts the N-source and P-body layers, and an enhanced P+ region at the base of the second trench.

Thin film transistor with three dimensional multichannel structure

Abstract: A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed. The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers. Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

Non-volatile random access memory cell constructed of silicon carbide

Abstract: A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.

Spatially resolved electrical measurements of SiO2 gate oxides using atomic force microscopy

Abstract: Using a modified atomic force microscope (AFM) with a conducting cantilever, we have investigated the dielectric strength of SiO2 gate oxide films. This has been achieved by spatially resolving the prebreakdown tunneling current flowing between the silicon substrate and tip. During AFM imaging a voltage ramp was applied to the tip at each image point so as to determine the local threshold voltage required to generate a small tunneling current in the oxide, without causing an irreversible electrical breakdown. For an oxide 12‐nm thick this voltage was found to vary by more than a factor of 2.7 over an area of 0.14 μm2, with a maximum value of 40.5 V. This suggests that the breakdown strength of conventional metal‐oxide‐silicon capacitors may not be limited by the intrinsic dielectric strength of the oxide, but by imperfections or nonuniformities in the Si/SiO2 structure. By preventing irreversible oxide breakdown during scanning, we can image the dielectric properties of oxide films with a lateral resoluti...

Silicon carbide switching device with rectifying-gate

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

Octadecyltrichlorosilane monolayers as ultrathin gate insulating films in metal‐insulator‐semiconductor devices

Abstract: In order to fabricate metal‐insulator‐semiconductor (MIS) devices with gate insulating films thinner than 5.0 nm, organic monolayers have been grafted on the native oxide layer of silicon wafers. We demonstrate that a single monolayer of octadecyltrichlorosilane with a 2.8 nm thickness allows to fabricate a silicon based MIS device with gate current density as low as 10−8 A/cm2 at 5.8 MV/cm, insulator charge density lower than 1010 cm−2, fast interface state density of the order of 1011 cm−2 eV−1, and dielectric breakdown field as high as 12 MV/cm. Moreover, this insulating film is thermally stable up to 450 °C.

Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection

Abstract: A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si3 N4 and SF.

Fabricating dual gate thin film transistors

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Method of controlling gate oxide thickness in the fabrication of semiconductor devices

Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

Vertical MOSFET having trench covered with multilayer gate film

Abstract: A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.

Manufacturing method for semiconductor devices with source/drain formed in substrate projection.

Abstract: A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. Formed below the drain, source, and channel regions is an element isolation section having the composition of the substrate intact. This eliminates the need for an oxide insulating layer below the transistor for easy manufacturing. Carriers generated in the channel region by ionization by collision can also be discharged to the substrate.

Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation

Abstract: A CMOS device is provided having a high concentration of nitrogen atoms at the SiO2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices In one embodiment, the process for providing the CMOS device resistant to hot carrier effects makes use of a sacrificial oxide layer through which the nitrogen atoms are implanted and is then removed Following removal of the sacrificial oxide layer, a gate oxide is grown giving a CMOS device having high nitrogen concentration at the SiO2 /Si interface In an alternate embodiment, nitrogen atoms are implanted through the final gate oxide using an implantation energy which does not damage the oxide layer

Device for preventing antenna effect on circuit

Abstract: A multi-level conductive interconnection for an integrated circuit with an antifuse device is formed, in and on a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. The antifuse device is formed from a thin dielectric between a first and second conductor and is connected to the integrated circuit, and is also connected to a ground reference through a silicon junction in the substrate. The large contact pad area is formed with a layer of metal, and is connected to the integrated circuit through the antifuse device, wherein the antifuse device electrically isolates the contact pad and the integrated circuit to prevent charge build-up during subsequent processing. There is further processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the antifuse device prevents charge build-up. A voltage is applied to the antifuse device to create a low impedance element, and formation of the integrated circuit is completed.

Semiconductor device and method of fabricating same

Abstract: There is disclosed a semiconductor device having a vertical channel MOS gate structure wherein grooves (40) are formed from the top surface of source regions (5) through a body (3) into an N diffusion region (2) and wherein buried gate electrodes (4) fill an inner part of said grooves (40) which is in face-to-face relation to the N diffusion region (2) across gate oxide films (13) while buried oxide films (15) including diffusion source impurities fill an inner part thereof which is in face-to-face relation to the source regions (5). The impurity concentration of the source regions (5) is distributed uniformly in the vertical direction of the grooves (40) and decreases lateraly away from the grooves (40). A current flows through the source region along the grooves and a resistance thereagainst is held small in an ON-state. The grooves may be formed with narrow spacing. The size reduction and high integration of the semiconductor device are achieved as well as reduction in ON-resistance.

Analysis and design of microwave amplifiers employing field‐emitter arrays

Abstract: An analysis of the microwave ( f≳1 GHz) properties of field‐emitter arrays (FEAs) and several representative medium power (10–100 W) microwave amplifiers employing FEAs is presented The FEA analysis is limited to parallel‐plate structures having discrete pointlike vertical emitter tips and gate apertures aligned to each tip A transmission line analysis of wave propagation in this structure is presented and used to evaluate the geometries and materials needed for microwave operation This analysis is used to investigate the performance capabilities and emitter requirements of both modulated‐emission linear beam tubes and microdevices based on FEAs Specific microtriode designs are used to investigate practical problems such as space charge and thermal effects Competitive performance should be achievable in gated‐emission linear beam tubes by using FEAs that perform at levels previously reported by several laboratories Existing FEA technology (currents of 10 μA per emitter, transconductances of 1 μS per emitter, 1 μm oxide thickness, and 3 μm emitter spacing) is suitable for use in cavity klystrodes(r) at frequencies through 10 GHz, and in moderately bunched beam (bunch width of 180°), octave‐bandwidth traveling‐wave‐tube applications through 3 GHz Extending the operating frequency and/or reducing the bunch width will require a larger ratio of transconductance to current Microtriodes operating at 10 GHz will benefit from a modified FEA structure and improved emitter performanceAn extra acceleration electrode must be added above the gate aperture to alleviate problems due to space charge between the gate and collector, and the gate oxide thickness must be increased to at least 2 μm A FEA incorporating these features and capable of producing 5 μS and 100 μA per emitter could generate 130 W from a 5‐mm‐wide device with 86 dB gain, 7% bandwidth, and 36% power added efficiency To allow higher gain and wideband operation, the transconductance at a given current must be increased A FEA capable of producing 5 μS at only 10 μA per emitter would result in a microtriode with more than 1 octave bandwidth, 45 W output power, 10 dB gain, and 34% power added efficiency Anode‐to‐case temperature differences of less than 100 °C appear possible in this device if BeO is used as the dielectric

Modeling oxide thickness dependence of charging damage by plasma processing

Abstract: Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model. >

Method for producing an active matrix substrate

Abstract: A method for producing an active matrix substrate using a thin film transistor having a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, a drain electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the semiconductor layer and the channel protective layer, and a source electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the method enhancing the transistor characteristics of the active matrix substrate with minimum leakage and the removal of an off-current generated from the presence of electrons and holes.

Method of making gate overlapped lightly doped drain for buried channel devices

Abstract: A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.

Thin film transistor having a lightly doped drain and an offset structure for suppressing the leakage current

Abstract: A thin film transistor wherein generation of a leakage current is prevented to improve the operation stability thereof and a method for manufacturing the same. A polysilicon layer is formed on an insulating layer. A gate insulating layer is formed on the polysilicon layer. A gate electrode having a barrier layer formed thereon is formed on the gate insulating layer. The sidewall surface portion of the gate electrode is anodic oxidized to form a metal oxide layer on the sidewall of the gate electrode. A lightly doped drain region having a lower impurity concentration than that of source and drain regions of the thin film transistor or an offset region wherein no impurity is doped is formed in a portion of the polysilicon layer under the metal oxide layer. The thin film transistor may be manufactured by a low temperature process, and leakage current is suppressed when a reverse bias voltage is applied. Therefore, the operation stability of the thin film transistor is improved.