Showing papers on "Gate oxide published in 1995"

Insulated-gate transistor having narrow-bandgap-source

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Six Ge1-x, Six Sn1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

Interface-trap generation at ultrathin SiO2 (4-6 nm)-Si interfaces during negative-bias temperature aging

Abstract: This article reports an investigation of the negative‐bias temperature instability in metal‐oxide‐silicon (MOS) systems with gate oxide thickness (Tox) in the range of 4.2–30 nm. The bias temperature aging was performed on p‐type samples with applied negative oxide fields (1.6–5.0 MV/cm) over a temperature range of 150–290 °C. The maximum aging time was 5000 h. The interface‐trap distribution was evaluated by the conductance technique. This time‐consuming method yields reliable results even in ultrathin oxides, if appropriate corrections are made. The interface‐trap generation and the concurrent fixed oxide charge can be expressed by simple empirical expressions. Their characteristic features are the inverse proportionality to oxide thickness (Tox) for the generated interface‐trap density (Nit) and no thickness dependence for the fixed charge generation. A general phenomenological model is proposed to explain these empirical expressions in terms of the diffusion‐reaction chemistry between hydrogenated tri...

Fabrication of 0.1 μm metal oxide semiconductor field‐effect transistors with the atomic force microscope

Abstract: Using the atomic force microscope (AFM), we have fabricated a metal oxide semiconductor field‐effect transistor (MOSFET) on silicon with an effective channel length of 0.1 μm. The lithography at the gate level was performed with the scanning tip of the AFM. The gate was defined by electric‐field‐enhanced selective oxidation of the amorphous silicon gate electrode. The electrical characteristics were reasonable with a transconductance of 279 mS/mm and a threshold voltage of 0.55 V.

Method of operating a single transistor non-volatile electrically alterable semiconductor memory device

Abstract: A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate. Programming is accomplished by electrons from the drain migrating through the channel region underneath the control gate and then by abrupt potential drop injecting through the first insulating layer into the floating gate.

Process for forming gate oxides possessing different thicknesses on a semiconductor substrate

Abstract: Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises growing a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions. The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Semiconductor electrode having improved grain structure and oxide growth properties

Abstract: The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V TM ) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors. An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300). The nitrogen doped amorphous silicon oxidizes at a slower rate than undoped amorphous silicon and has less inherent stress resulting in thinner a capacitor dielectric (308) of fewer defects. The capacitor plates (304 and 306) maintain their microcrystalline structure throughout subsequent temperature cycling resulting in increased capacitor area.

Method for producing semiconductor device with a gate insulating film consisting of silicon oxynitride

Abstract: In an insulated gate type field effect semiconductor device having a thin silicon semiconductor film, the gate insulating film that covers the active layer is a thin film consisting essentially of silicon, oxygen and nitrogen. In the gate insulating film in the device, the nitrogen content is made the largest in the interface between the film and the adjacent gate electrode, and the material constituting the gate electrode is prevented from being diffused into the gate insulating film. In the film, the nitrogen content is made the largest in the interface between the film and the adjacent active layer, and hydrogen ions, etc. are prevented from being diffused from the active layer into the gate insulating film. Prior to the formation of the gate insulating film, the surface of the active layer is irradiated to laser rays or intense rays comparable to laser rays, so as to be oxidized or nitrided.

Transistor with low resistance tip and method of fabrication in a CMOS process

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Process of making EEPROM memory device having a sidewall spacer floating gate electrode

Abstract: An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Process for producing a semiconductor device having a single thermal oxidizing step

Abstract: A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance

Abstract: We present a physically based continuous analytical MOSFET model for submicrometer devices that includes polysilicon depletion effect. It is shown that simple modification to standard MOSFET circuit models is all that is needed to account for the polydepletion effect. The new model accurately predicts, both measured and 2-D simulated, I-V, and C-V characteristics of submicrometer MOSFET's with polydepletion effect over a range of polysilicon gate concentration, N/sub p/, down to 5/spl times/10/sup 18/ cm/sup 3/. It is found that neglecting the polydepletion effect for devices with nondegenerate gate doping leads to nonphysical model parameters and causes large errors in the capacitance modeled results. The new model has been implemented in the circuit simulator SPICE. Since both device current and capacitance degrade due to polydepletion effect, its impact on circuit performance is studied using inverter type circuits with different loading conditions. SPICE simulations show that for 0.35 /spl mu/m CMOS technology (gate oxide thickness, t/sub ox/=70 /spl Aring/) the increase in the delay time for chain of inverters is 3.5% for N/sub p/=2/spl times/10/sup 19/ cm/sup -3/ (for both nand p-channel devices) compared to N/sub p/=5/spl times/10/sup 19/, cm/sup -3/. For a given t/sub ox/ and nondegenerate value of N/sub p/, lowering the channel length helps to reduce the polydepletion effect and hence circuit performance degradation. However, reducing the power supply, for low power operation, enhances the polydepletion effect. >

Non-volatile semiconductor memory device having a metal-insulator-semiconductor gate structure and method for fabricating the same

Abstract: There is provided a metal-insulator-semiconductor gate insulating structure involved in a non-volatile memory device. A first insulating layer formed on the semiconductor substrate has a first dielectric constant e 1 and a first thickness of t 1 . A second insulating layer formed on the first insulating layer layer has a second dielectric constant e 2 and a second thickness of t 2 . A gate electrode of a metal layer is formed on the second insulating layer. The first and second dielectric constants e 1 and e 2 and the first and second thicknesses t 1 and t 2 satisfy the conditions of 20≦e 2 /e 1 , and t 2 /t 1 ≦e 2 /e 1 .

Controlled nitrogen incorporation at the gate oxide surface

Abstract: Nitrogen has been incorporated selectively at the top surface of a conventional thermal gate oxide by nitridation with a remote He–N2 plasma at low temperatures, 23 and 300 °C. On‐line Auger electron spectroscopy (AES) has been used to characterize the process. A peak shift in the Si‐LVV feature establishes that the nitrogen is bonded to the silicon. The concentration of nitrogen can be varied by a combination of substrate temperature and duration of plasma exposure. Ex situ glancing‐angle x‐ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) confirm that the nitrogen is confined to the immediate vicinity of the surface. Rapid thermal annealing (RTA) of the nitrided oxide at 900 °C in N2 and N2O does not change the N content.

Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR. The cathode and cathode gate of the second SCR are connected to the second power terminals. The anode of the second SCR is connected to its associated I/O buffering pads. The anode gate of the second SCR is connected to the first power terminal. The ESD circuit also comprises an NMOS transistor having drain, source, gate, and bulk terminals. The NMOS transistor's gate, source and bulk terminals are connected to the second power terminals. The NMOS transistor's drain terminal is connected to the anode gate of the second SCR.

Split-gate vertically oriented EEPROM device and process

Abstract: A split-gate EEPROM transistor includes a channel region (22) formed in a vertically disposed semiconductor body (58) and residing intermediate to a drain region (26) and a source region (24). A select gate electrode (28) is horizontally disposed on a semiconductor substrate (20). A floating gate electrode (30) resides adjacent to the channel region (22) and overlies the select gate electrode (28). A control gate electrode (32) resides adjacent to the control gate electrode (30) and also overlies the select gate electrode (28). In operation, the select gate electrode (28) regulates the flow of electrical charge from the source region (24) into the channel region (22), and provides a field plate electrical isolation for adjacent memory cells in an EEPROM array.

Oxidation of silicon: the VLSI gate dielectric

Abstract: Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale. The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that Pb concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen. Finally, the roles of contamination, particles, metals, hydrocarbons etc. are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above.

Method of fabricating thin film semiconductor integrated circuit

Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.

Process for fabricating a fully self-aligned soi mosfet

Abstract: A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's

Abstract: Previously, we proposed n/sup +/-p/sup +/ double-gate SOI MOSFET's, which have n/sup +/ polysilicon for the back gate and p/sup +/ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n/sup +/ and p/sup +/ polysilicon gates: V/sub th1/ and V/sub th2/, respectively. V/sub th1/ is a function of the gate oxide thickness t/sub Ox/ and SOI thickness t/sub Si/ and is about 0.25 V when t/sub Ox//t/sub Si/=5, while V/sub th2/ is insensitive to t/sub Ox/ and t/sub Si/ and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 /spl mu/m gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing. >

Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range

Abstract: The size of an active pixel sensor cell is reduced by utilizing a single split-gate MOS transistor and a reset gate. The split-gate transistor includes an image collection region which is formed in the drain region and electrically connected to the floating gate of the transistor. Light energy striking the image collection region varies the potential of the floating gate which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.

Vertical field effect transistor with a trench structure

Abstract: A polycrystalline silicon film which is to be a channel is in a trench provided in a main surface of a silicon substrate. A gate insulating film is on the periphery of a polycrystalline silicon film. A gate electrode is on the periphery of the gate insulating film. A silicon oxide film is on the periphery of the gate electrode. A source/drain film is on the periphery of the silicon oxide film. A silicon oxide film is on the periphery of the source/drain film. A source/drain film is electrically connected to the polycrystalline silicon film. A source/drain film is electrically connected to the polycrystalline silicon film. Since the polycrystalline silicon film extends along the depth direction of trench, a channel length can be sufficient to prevent a short channel effect. Also, compared to the case in which an epitaxial layer is used as a channel, since the polycrystalline silicon film is used as a channel, the time required for manufacturing the device can be shortened.

AlxGa1−xAs–GaAs metal–oxide semiconductor field effect transistors formed by lateral water vapor oxidation of AlAs

Abstract: Data are presented demonstrating a GaAs‐based metal–oxide semiconductor field effect transistor employing in the gate region a laterally formed native oxide of AlAs. The gate oxide, formed by a water vapor process, is similar to that used successfully in recently developed semiconductor laser devices. The transistors described here represent an extension of the ‘‘wet’’ oxidation Al‐based III–V native oxide technology employed successfully in light‐emitting and laser devices.

Liquid crystal display device having storage capacitors of increased capacitance and fabrication method therefor

Abstract: A liquid crystal display (LCD) device includes: a plurality of gate lines and a plurality of data lines arranged in the form of a matrix; a plurality of transistors each having a gate, a source and a drain, and each disposed at an intersecting point of the lines; a plurality of pixel electrodes connected to the drain electrodes of the respective transistors; and a plurality of capacitors formed on the pixel electrodes. The capacitor includes a capacitor electrode, a gate insulating layer, a semiconductor layer and a protective insulating layer. The semiconductor layer of the capacitor is composed of the same material as that of a semiconductor region of the transistor. An etch stop layer is used for protecting a gate insulating layer during etching a protective insulating layer situated above the gate insulating layer. For the etch stop layer, an amorphous silicon layer or a metal layer are used. By virtue of using the etch stop layer, the capacitor electrodes can be spaced closer together than in conventional LCD devices, thereby advantageously resulting in increased storage capacitance and improved displayed image quality.

Method of fabricating a self-aligned DMOS transistor device using SiC and spacers

Abstract: A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconductor layer; and patterning the gate electrode layer to form a gate electrode portion adjacent to an edge of the patterned refractory dielectric layer. Preferably the step of conformally depositing the gate electrode layer includes depositing an electrically conductive layer having the same thickness as a combined width of the first and second spacers. In one embodiment the semiconductor layer includes silicon carbide, the patterned refractory dielectric layer includes silicon dioxide, the spacers include silicon nitride, and the gate electrode layer includes polysilicon.

Trench MOSFET with multi-resistivity drain to provide low on-resistance

Abstract: A MOSFET switch with a gate formed in a trench has a drain which includes a region of relatively high resistivity adjacent the trench and a region of relatively low resistivity further away from the trench. The drain may also include a "delta" layer having even lower resistivity in a central region of the MOSFET cell. The high resistivity region limits the strength of the electric field at the edge of the trench (particularly where there are any sharp corners) and thereby avoids damage to the gate oxide layer. The central "delta" layer helps to insure that any breakdown will occur near the center of the MOSFET cell, away from the gate oxide, and to lower the resistance of the MOSFET when it is in an on condition.

Method of forming high pressure silicon oxynitride gate dielectrics

Abstract: A silicon oxynitride (oxynitride) dielectric layer is presented using a process in which nitrogen is incorporated into the dielectric as it is grown upon a silicon substrate. The oxynitride layer is grown at elevated temperature and pressure in an ambient containing N 2 O and/or NO. A MOS gate dielectric is advantageously formed from the oxynitride dielectric layer with a sufficient nitrogen concentration near the interface between a boron-doped polysilicon gate electrode and the gate dielectric as to prevent boron atoms from penetrating into the gate dielectric. Further, the oxynitride layer contains a sufficient nitrogen concentration near the interface between the gate dielectric and a silicon substrate as to reduce the number of high-energy electrons injected into the gate dielectric which become trapped in the gate dielectric. Nitrogen atoms in the gate dielectric near the interface between the boron-doped polysilicon gate electrode and the gate dielectric physically block boron atoms, preventing them from penetrating into the gate dielectric. Nitrogen atoms and silicon atoms form strong Si--N bonds at the interface between the gate dielectric and the silicon substrate, helping ensure injected electrons are not easily trapped in the oxynitride dielectric layer.

Method of maufacturing a semiconductor device having a low resistance gate electrode

Abstract: A method for manufacturing a semiconductor device, e.g., an LDD transistor, which includes the steps of forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the gate insulating layer, forming a silicide layer on the polysilicon layer, etching the silicide layer to form a gate-patterned silicide layer, and over-etching the silicide layer to partially etch the polysilicon layer, to thereby form a step in the polysilicon layer, forming an oxidation-prevention spacer on sidewalls of the gate-patterned silicide layer and sidewalls of the polysilicon layer exposed by the step, etching the polysilicon layer, using the oxidation-prevention spacer as an etching mask, to thereby form a gate-patterned polysilicon layer, the gate-patterned silicide layer and the gate-patterned polysilicon layer together comprising a gate electrode, thermally oxidizing exposed portions of the gate insulating layer and exposed portions of the polysilicon layer, to thereby form an oxide layer, and, ion-implanting impurities into the semiconductor substrate, using the resultant structure as an ion-implantation mask, to thereby form source/drain regions in the semiconductor substrate, on opposite sides of the gate electrode.

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.