Showing papers on "Gate oxide published in 1996"

A ferroelectric transparent thin‐film transistor

Abstract: Operation is demonstrated of a field‐effect transistor made of transparant oxidic thin films, showing an intrinsic memory function due to the usage of a ferroelectric insulator. The device consists of a high mobility Sb‐doped n‐type SnO2 semiconductor layer, PbZr0.2Ti0.8O3 as a ferroelectric insulator, and SrRuO3 as a gate electrode, each layer prepared by pulsed laser deposition. The hysteresis behavior of the channel conductance is studied. Using gate voltage pulses of 100 μs duration and a pulse height of ±3 V, a change of a factor of two in the remnant conductance is achieved. The dependence of the conductance on the polarity of the gate pulse proves that the memory effect is driven by the ferroelectric polarization. The influence of charge trapping is also observed and discussed.

Methods for forming liquid crystal displays including thin film transistors and gate pads having a particular structure

Abstract: A method for forming a liquid crystal display includes the steps of depositing a first metal layer on a substrate, and depositing a second metal layer on the first metal layer opposite the substrate. The first and second metal layers are patterned to provide a gate electrode on a TFT area of the substrate and to provide a gate pad on a pad area of the substrate. An insulating layer is formed on the gate electrode and on the gate pad, and on the substrate, and a semiconductor layer is formed on the insulating layer opposite the gate electrode wherein the semiconductor layer includes a channel region opposite the gate electrode and first and second spaced apart source/drain regions separated by the channel region. First and second spaced apart metal source/drain electrodes are formed on the respective first and second spaced apart semiconductor source/drain regions, and a protective layer is formed on the exposed portion of the first semiconductor layer opposite the substrate, on the first and second metal source/drain electrodes opposite the substrate, and on the insulating layer opposite the gate pad. A first contact hole is formed in the protective layer exposing a portion of one of the source/drain electrodes, and a second contact hole is formed in the protective layer and the insulating layer exposing a portion of the gate pad wherein the second contact hole exposes only a surface portion of the gate pad opposite the substrate. A transparent conductive layer is formed on the protective layer opposite the substrate, and the transparent conductive layer is patterned to form a pixel electrode electrically connected to the exposed portion of the source/drain electrode and to the exposed portion of the gate pad.

Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

Fast and long retention-time nano-crystal memory

Abstract: A threshold-shifting, single transistor memory structure with fast read and write times and long retention time is described. The structure consists of a silicon field-effect transistor with nano-crystals of germanium or silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 2-5 nm size nano-crystals which are separated from each other by greater than 5 nm of SiO/sub 2/ and from the inversion layer of the substrate surface by less than 5 nm of SiO/sub 2/. Direct tunneling of charge from the inversion layer and its storage in the nano-crystal causes a shift in the threshold voltage which is detected via current sensing. The nano-crystals are formed using implantation and annealing or using direct deposition of the distributed floating gate region. Threshold shift of 0.3 V is obtained in Ge-implanted devices with 2 nm of SiO/sub 2/ injection layer by a 4 V write pulse of 300 ns duration. The nano-crystal memories achieve improved programming characteristics as a nonvolatile memory as well as simplicity of the single poly-Si-gate process. The V/sub T/ window is scarcely degraded after greater than 10/sup 9/ write/erase cycles or greater than 10/sup 5/ s retention time. Nano-crystal memories are promising for nonvolatile memory applications.

1.5 nm direct-tunneling gate oxide Si MOSFET's

Abstract: In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

Soft breakdown of ultra-thin gate oxide layers

Abstract: The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Gate oxide scaling limits and projection

Abstract: MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient for MOSFET scaling to 0.05 /spl mu/m.

Concurrent thermal and electrical modeling of sub‐micrometer silicon devices

Abstract: High electric fields, that are characteristic of sub‐micron devices, produce highly energetic electrons, lack of equilibrium between electrons, optical phonons, and acoustic phonons, and high rates of heat generation. A simple coupled thermal and electrical model is developed for sub‐micron silicon semiconductor devices consisting of the hydrodynamic equations for electron transport and energy conservation equations for different phonon modes. An electron Reynolds number is proposed and used to simplify the electron momentum equation. On a case study of the metal‐oxide‐semiconductor field‐effect transistor with 0.24 μm gate length, the calculated transconductance of 0.175 1/Ω m agreed well with measured value of 0.180 1/Ω m at 2 V drain voltage. The maximum electron temperature is found to occur under the drain side of the gate where the electric field is the highest. Comparison with experimental data shows the predictions of optical and acoustic phonon temperature distributions to have the correct trend and the observed asymmetric behavior. Increase in substrate boundary temperature by 100 °C reduces the drain current by 17% and decreases the maximum electron temperature by 8%. The first effect increases device delay and the second effect decreases the possibility of device degradation by charge trapping in the gate oxide.

Non-volatile semiconductor memory

Abstract: Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

Si-Ge CMOS semiconductor device

Abstract: To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer 11 of Si 1−x Ge x inhibiting boron diffusion is provided between the strongly doped layer 10 and the intrinsic surface region 7 , for example with x=0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.

Ultrathin oxynitride structure and process for VLSI applications

Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Very-fast transmission line pulsing of integrated structures and the charged device model

Abstract: Transmission line pulsing (TLP) is well-established for the IV-characterization of ESD-protection elements. There still is a significant gap between the performance of present TLP-systems and the demands of the Charged Device Model (CDM). A very-fast, narrow-pulse (>3.5 ns), high-current TLP (VF-TLP) is designed to reduce this gap. It is feasible to study the pulsed breakdown of gate oxides and to determine at least the quasi-static IV-characteristics of input structures. Gate oxide breakdown is monitored within the first 6 ns of stress. Correlation with nn-CDM tests is achieved in terms of the failure signature. However, the failure thresholds of VF-TLP and nn-CDM do not correlate.

Method of making thin film transistor using lateral crystallization

Abstract: A highly reliable thin-film transistor (TFT) having excellent characteristics. A silicon film is grown laterally by adding a metal element such as nickel to promote crystallization. A crystal grain boundary is formed parallel to a gate electrode and around the center of the gate electrode. Thus, the grain boundary does not exist around the interface between the drain and the channel formation region. At this interface, a large stress is induced by a large electric field. The concentration of the metal element is low around the interface between the drain and the channel formation region. Therefore, the leakage voltage is small. Also, when a reverse voltage is applied to the gate electrode, the leakage current is small.

PMOS single-poly non-volatile memory structure

Abstract: A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon floating gate is separated from the N-well by a thin oxide layer. A P-type diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. Within this P-type diffusion area lies an N-type diffusion area which serves as the control gate for the cell. The P-type diffusion region electrically isolates the control gate from the N-well such that voltages may be applied to the control gate in excess of those applied to the N-well without creating a current path from the control gate to the N-well. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions so as to cause the tunneling of electrons from the P+ drain region of the cell to the floating gate. In some embodiments, an additional P-type diffusion region underlying the floating gate and separated therefrom by a layer of tunnel oxide serve as an erase gate for the memory cell. In such embodiments, erasing of the cell is accomplished by causing electrons to tunnel from the floating gate to the erase gate.

Gate dielectric based on oxynitride grown in N2 O and annealed in NO

Abstract: A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N 2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO 2 interface than either N 2 O oxynitride or nitridation of SiO 2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N 2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.

Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages

Abstract: The widely accepted universal dependence of N- and P-MOSFETs carrier mobility on effective vertical field E eff = (ηQ inv + Q b ) ϵ Si has been re-examined. New empirical mobility models for both electrons and holes expressed in terms of Tox, Vt and Vg explicitly are formulated. New empirical mobility models are confirmed with experimental data taken from devices of different technologies. It is also shown that the hole mobility of both the surface and buried channel P-MOSFETs can be unified for the first time by a single universal mobility equation, rather than two separate equations as previously thought necessary.

Semiconductor device comprising trench EEPROM

Abstract: Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors. The device configuration as above achieves reduction in area of the gate electrode portions (23) and further reduction in each level difference between both regions having and not having the gate electrode portion (23). Thus, reduction in level difference of each memory cell is achieved while reduction in area of each memory cell is ensured.

Neuron adhesion on a silicon chip probed by an array of field-effect transistors.

Abstract: Adhesion of neurons to surfaces in biological tissue (eg, to glia cells, in synapses) or in cell culture (on glass or silicon) may seriously change the features of the electrical signals Transmembrane ion currents have to flow along the narrow cleft between membrane and surface They give rise to a drop of voltage that may affect, in turn, the ion channels [1] In the present paper we show that the electrical properties of cell adhesion can be probed by taking advantage of the neuron-silicon junction [2,3] We place the neuron on an oxidized surface of silicon with an integrated array of field-effect transistors with open metal-free gate oxide [cf Fig 1(a)] An ac voltage is applied to the neuron This voltage couples into the cleft through the conductance and the capacitance of the membrane The resulting extracellular voltage profile is evaluated from the modulation of the source-drain currents Neuron-silicon assembly— A view of the silicon chip is shown in Fig 2(a) The 16 metal-free transistors are arranged in two rows Their distance is 52 mm The area of the transistor channels is 18 mm 3 18 mm Zones of recessed oxide separate the transistors (They give rise to a modulation of the surface profile by about 250 nm) Each drain has its own lead All transistors share a common source Care was taken that the geometric aspects and the electrical properties (bias voltages, sensitivity, and threshold voltage) of the transistors were similar to the larger transistors, used in previous experiments [2,3] The chip s10 mm 3 10 mmd was stuck on a plate with copper leads After wedge bonding a Plexiglas chamber was attached We cleaned the exposed surface of the chip by hot basic hydrogen peroxide The gate region was coated with poly-L-lysine The chamber was filled with culture medium (Leibowitz-15) Retzius cells from the segmental ganglia of the leech hirudo medicinalis were isolated [4] and treated with collagenase and dispase before the experiment Then a neuron was placed on the array as illustrated in Fig 2(b) We kept the bath on ground potential using an AgyAgCl electrode [cf Fig 3(b)] A bias voltage of VES › 230 V was applied between electrolyte and bulk silicon The source was kept at bulk potential The drain-source voltage was VDS › 220 V, which caused a source-drain current of about ID › 50 mA A change DVES › 10 mV of the voltage between electrolyte and source induced a current modulation of DID › 2045 mA as checked before the attachment of a neuron The neuron was contacted with a AgyAgCl electrode by fusing the membrane with a patch pipette filled with electrolyte [3,5] The intracellular potential was held at ‐50 mV Cell impedance—We superposed ac stimuli of 15 mV amplitude to the holding potential No action potentials were elicited under these conditions We measured the complex amplitudes V P of the voltage and I P of the current at the head of the pipette [Fig 3(a)] using two lock-in amplifiers A Nyquist plot of the impedance Z › V P yI P of an attached neuron is shown in Fig 3(b) in a frequency range from 1 to 15 000 Hz The double

Sourceless floating gate memory device and method of storing data

Abstract: A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region (64) formed in a substrate (62); an oxide overlying and associated with the drain region (64); and a floating gate (66) overlying the oxide. Upon application of a voltage to the drain (64), a current between the drain (64) and substrate (62) is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication

Abstract: A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member. A second source and second drain region of the second conductivity type are formed in the first source and first drain regions, respectively. The second source and second drain regions are formed in alignment with the outer edges of the second sidewall spacers.

Method of making self-aligned halo process for reducing junction capacitance

Abstract: A method for forming an LDD structure using a self-aligned halo process is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A gate electrode is formed overlying the gate silicon oxide layer. A silicon oxide layer is grown on the sidewalls of the gate electrode and silicon nitride spacers are formed on the sidewalls of the silicon oxide layer. First ions are implanted into the semiconductor substrate and the substrate is annealed whereby heavily doped source and drain regions are formed within the semiconductor substrate not covered by the gate electrode and the silicon oxide and silicon nitride spacers. An oxide layer is grown over the heavily doped source and drain regions. Thereafter, the silicon nitride spacers are removed. Second ions are implanted to form lightly doped regions in the semiconductor substrate not covered by the oxide layer. Third ions are implanted to form a halo having opposite dosage and a deeper junction than the lightly doped regions. An insulating layer is deposited over the surface of the substrate. An opening is provided through the insulating layer to one of the source and drain regions. A conducting layer is deposited overlying the insulating layer and within the opening and patterned completing the fabrication of the integrated circuit device.

Semiconductor device having a gate electrode in a grove and a diffused region under the grove

Abstract: A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.

High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs

Abstract: Results of the high-frequency AC characteristics of 1.5 nm direct-tunneling gate oxide MOSFET's were shown for the first time. Very high cutoff frequencies of more than 150 GHz were obtained at gate lengths of sub-0.1 /spl mu/m regime due to the high transconductance. Excellent NF/sub min/ value of 0.51 dB was obtained at high-frequency operation of 2 GHz. Also, good operation of the 1.5 nm gate oxide CMOS ring oscillator has been confirmed.

EEPROM having coplanar on-insulator FET and control gate

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Correlation between inversion layer mobility and surface roughness measured by AFM

Abstract: The correlation between inversion layer mobility of MOSFET's and surface micro-roughness of the channel has been studied using split CV measurements and AFM analysis. The mobility at high normal field decreases with increasing the surface roughness over a wide range of roughness from 0.3 nm to 4.3 nm (RMS). The trend is the same even for very thin gate oxides down to 3 nm. Careful AFM measurements are used to show that the gate oxide thickness doesn't affect the surface roughness, supporting the independence of mobility on the gate oxide thickness.

Punch-through field effect transistor

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region (44) and drain region (40). Forward conduction occurs through an inversion region between the source region (44) and drain region (40). Blocking is achieved by a gate controlled depletion barrier. Located between the source (44) and drain (40) regions is a fairly lightly doped body region (42). The gate electrode (52A), located in a trench (50A), extends through the source (44) and body (42) regions and in some cases into the upper portion of the drain region (40). The dopant type of the polysilicon gate electrode (52A) is the same type as that of the body region (42). The body region (42) is a relatively thin and lightly doped epitaxial layer grown upon a higly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Degradation of oxynitride gate dielectric reliability due to boron diffusion

Abstract: In this letter, we report on the impact of the suppression of boron diffusion via nitridation of SiO2 on gate oxide integrity and device reliability SiO2 subjected to rapid thermal nitridation in pure nitric oxide (NO) is used to fabricate thin oxynitride gate dielectrics Both n+ polycrystalline silicon (polysilicon) gated n‐MOS (metal–oxide semiconductor) and p+‐polysilicon gated p‐MOS devices were subjected to anneals of different times to study the effect of dopant diffusion on gate oxide integrity As expected, an advanced oxynitride gate dielectric will effectively alleviate the boron‐penetration‐induced flatband voltage instability in p+‐polysilicon gated p‐MOS capacitors due to the superior diffusion barrier properties However, such improvements are observed in conjunction with some degradation of the oxide reliability due to the boron‐blocking/accumulation inside the gate dielectric Results show that even though the oxide quality is slightly degraded for NO‐nitrided SiO2 with p+‐polysilicon ga

Thin gate oxide damage due to plasma processing

Abstract: Plasma processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modelled as damage produced by constant-current (or voltage) electrical stress. Plasma processing causes MOSFET parameter degradation, from which one can deduce the plasma charging current. Since the scattering of post-damage device parameters is due to a reproducible variation of stress current across the wafer, one can easily analyse the effect of device geometry on damage by comparing test structures in the same die rather than the averages over a wafer. We have developed a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of the charging current. The model successfully predicts the oxide thickness dependence of plasma charging. It is shown that plasma acting on a very thin oxide during processing may be modelled essentially as a current source. Thus the damage will not be greatly exacerbated as the oxide thickness is further reduced in the future. Although annealing in forming gas can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. The protection diode should be forward biased during processing to safely protect the gate oxide. In CMOS circuits, the drains of the driver circuit can generally act as adequate protection diodes for the oxide regardless of N or P substrate and the polarity of the plasma charging current. The plasma stress current can be reduced by reducing the ion density, which is unfortunately linked to the etch rate or directionality, or by reducing the electron temperature. Maintaining a very uniform plasma over the surface of the wafer, reducing the plasma charging current during the over-etch time and judicious use of protection diode and antenna design rules will reduce plasma damage to an acceptable level for ULSI production even for very thin gate oxides.

Fabrication process for thin film transistors in a display or electronic device

Abstract: A fabrication process for a thin film transistor including, in the first process step, performing semiconductor layer formation processing, crystallization processing, and first gate insulator formation processing without exposing the substrate to atmosphere. In the second process step, performing rapid thermal processing of the first gate insulator layer and the semiconductor layer. In the third process step, performing patterning of the first gate insulator layer and the semiconductor layer. In the fourth process step, performing cleaning by etching the surface of the first gate insulator layer which has been contaminated by the resist mask. In the fifth process step, performing hydrogenation processing followed by formation of the second gate insulator layer on the surface of the first gate insulator layer.

Low temperature method of forming gate electrode and gate dielectric

Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.