Showing papers on "Gate oxide published in 1998"

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

Abstract: This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Zirconium and/or hafnium oxynitride gate dielectric

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

MOS Scaling: Transistor Challenges for the 21st Century

Abstract: Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistors (see Table 1). We show that traditional SiO2 gate dielectrics will reach fundamental leakage limits, due to tunneling, for an effective electrical thickness below 2.3 nm. Experimental data and simulations are used to show that although conventional scaling of junction depths is still possible, increased resistance for junction depths below 30 nm results in performance degradation. Because of these limits, it will not be possible to further improve short channel effects. This will result in either unacceptable off-state leakage currents or strongly degraded device performance for gate lengths below 0.10μm. MOS transistor limits will be reached for 0.13μm process technologies in production during 2002. Because of these problems, new solutions will need to be developed for continued transistor scaling. We discuss some of the proposed solutions including high dielectric constant gate materials and alternate device architectures.

Generalized scale length for two-dimensional effects in MOSFETs

Abstract: We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.

A folded-channel MOSFET for deep-sub-tenth micron era

Abstract: Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported To improve the short channel effect immunities, a novel folded channel transistor structure is proposed The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short

Intermixing at the tantalum oxide/silicon interface in gate dielectric structures

Abstract: Metal oxides with high dielectric constants have the potential to extend scaling of transistor gate capacitance beyond that of ultrathin silicon dioxide. However, during deposition of most metal oxides on silicon, an interfacial region of SiOx can form that limits the specific capacitance of the gate structure. We have examined the composition of this layer using high-resolution depth profiling of medium ion energy scattering combined with infrared spectroscopy and transmission electron microscopy. We find that the interfacial region is not pure SiO2, but is a complex depth-dependent ternary oxide of Si–Tax–Oy with a dielectric constant at least twice that of pure SiO2 as inferred from electrical measurements. High-temperature annealing crystallizes the Ta2O5 film and converts the composite oxide to a more pure SiO2 layer with a lower capacitance density. Using low postanneal temperatures, a stable composite oxide structure can be obtained with good electrical properties and an effective SiO2 thickness of...

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

Abstract: We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.

High-voltage accumulation-layer UMOSFET's in 4H-SiC

Abstract: A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 /spl mu/m drift region), a specific on-resistance of 15.7 m/spl Omega/-cm/sup 2/ at room temperature, and a gate oxide field of 3 MV/cm.

Method of metal/polysilicon gate formation in a field effect transistor

Abstract: A method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) of the semiconductor substrate adjacent to the source and drain regions. A masking layer (136) is formed, covering substantially all the semiconductor substrate. Portions of the masking layer are then selectively removed to expose at least selected portions of the polysilicon gate. Selected portions of the polysilicon gate are partially etched. By selective electroless metal deposition, a metal layer (146) is formed on the etched selected portions of the polysilicon gate. In an alternative embodiment, the masking layer is removed before selective deposition of the electroless metal, so that electroless metal is simultaneously deposited on the polysilicon gate and the source region and the drain region.

Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher

Abstract: A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises: a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O 2 gasses, and applying a first TCP Power and a first Bias power; b) in STEP 2, etching the hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; c) in STEP 3--stripping the bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power; d) in STEP 4--etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.

Shallow trench isolation of MOSFETS with reduced corner parasitic currents

Abstract: A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which rounds off the corners and also reduces the effect of tensile stresses caused by the densified trench filler material. The method selectively exposes the corner regions to an oxidation whereby the formation of an oxide birdsbeak modulates the corners and introduces a compressive stress component in the corner region. Several variations of the procedure are disclosed, including embodiments wherein birdsbeaks extending in both a vertical and horizontal directions from the corners are employed. The channel and gate oxide edges of MOSFETs extend to these corners. By attenuating the abrupt corners and reducing the mechanical stresses, gate oxide integrity is improved and anomalous sub-threshold currents of MOSFETs formed are abated.

Conducting atomic force microscopy for nanoscale electrical characterization of thin SiO2

Abstract: In this work, we demonstrate the applicability of conducting atomic force microscopy (AFM) for the quantitative electrical characterization of thin (3–40 nm) SiO2 films on a nanometer scale length. Fowler–Nordheim (F–N) tunneling currents on the order of 0.02–1 pA are measured simultaneously with the oxide surface topography by applying a voltage between the AFM tip and the silicon substrate. Current variations in the F–N current images are correlated to local variations of the oxide thickness on the order of several angstroms to nanometers. From the microscopic current–voltage characteristics the local oxide thickness can be obtained with an accuracy of ±0.3 nm. Local oxide thinning of up to 3.3 nm was found at the edge between gate oxide and field oxide of a metal-oxide-semiconductor capacitor with a 20-nm-thick gate oxide.

Tunneling leakage current in oxynitride: dependence on oxygen/nitrogen content

Abstract: It is widely known that the addition of nitrogen in silicon oxide, or the addition of oxygen in silicon nitride, affects its reliability as a gate dielectric. The authors examine the gate leakage current as a function of the oxygen and nitrogen contents in ultrathin silicon oxynitride films on Si substrates. It is shown that, provided that electron tunneling is the dominant current conduction mechanism, the gate leakage current in the direct tunneling regime increases monotonically with the oxygen content for a given equivalent oxide thickness (EOT), such that pure silicon nitride passes the least amount of current while pure silicon oxide is the leakiest.

CMOS semiconductor devices and method of formation

Abstract: In one embodiment, a metal layer (18) is formed over a gate dielectric layer (14, 16) on a semiconductor substrate. A masking layer (20) is patterned to mask a portion of the metal layer (18). An exposed portion of the metal layer (18) is nitrided to form a conductive nitride layer (24). The masking layer (20) is removed and the conductive nitride layer (24) is patterned to form a first gate electrode (23) having a first work function value, and the conductive layer (18) is patterned to form a second gate electrode (25) having a second work function value which is different from that of the first work function value.

Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region

Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Abstract: Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I/sub g/ versus V/sub g/ characteristics for the p/sup +//pMOSFET are essentially identical to those for the n/sup +//nMOSFET; however, when measured in inversion, the p/sup +//pMOSFET exhibits much lower gate current for the same |V/sub g/|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p/sup +//pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p/sup +/-polysilicon gate; and (3) conduction band electron tunneling from the p/sup +/-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p/sup +//pMOSFET, with one of them dominating in a certain voltage range.

Flash memory with nanocrystalline silicon film floating gate

Abstract: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

Stacked high-ε gate dielectric for gigascale integration of metal–oxide–semiconductor technologies

Abstract: Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of metal–oxide–semiconductor technologies to sub-0.25 μm feature size. A major hurdle in the gate dielectric scaling using conventional thermally grown SiO2 has been excessive tunneling that occurs in ultrathin (<25 A) SiO2. High dielectric constant materials such as Ta2O5 have been suggested as a substitute for SiO2. However, these materials have high concentrations of bulk fixed charge, unacceptable levels of Si–Ta2O5 interface trap states, and low silicon interface carrier mobilities. This letter summerizes an elegant solution to these issues through synthesis of a thermally grown SiO2(15 A)–Ta2O5(30 A)–SiO2(5–10 A) dielectric with improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold, saturation, and drive currents.

Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM

Abstract: The degradation of thin tunnel gate oxide under constant Fowler-Nordheim (FN) current stress was studied using flash EEPROM structures. The degradation is a strong function of the amount of injected charge density (Q/sub inj/), oxide thickness, and the direction of stress. Positive charge trapping is usually dominant at low Q/sub inj/ followed by negative charge trapping at high Q/sub inj/, causing a turnaround of gate voltage and threshold voltage. Interface trap generation continues to increase with increasing stress, as evidenced by subthreshold slope and transconductance. Gate injection stress creates more positive charge traps and interface traps than does substrate injection stress. Oxide degradation gets more severe for thicker oxide, due to more oxide charge trapping and interface trap generation by impact ionization. A simple model of oxide degradation and breakdown was established based on the experimental results. It indicates that the damage in the oxide is more serious near the anode interface by impact ionization and oxide breakdown is also closely related to surface roughness at the cathode interface. When all the damage sites in the oxide connect and a conductive path between cathode and anode is formed, oxide breakdown occurs. The damage is more serious for thicker oxide because a thicker oxide is more susceptible to impact ionization.

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

Abstract: This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

Mos transistor with dual metal gate structure

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Pseudo silicon on insulator MOSFET device

Abstract: A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

Tunable threshold SOI device using isolated well structure for back gate

Abstract: To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Abstract: Semiconductor devices having a metal gate electrode and a titanium or tantalum nitride gate dielectric barrier layer and processes for fabricating such devices are provided. The use of a metal gate electrode along with a titanium or tantalum nitride gate dielectric barrier layer can, for example, provide a highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.

Model for the current–voltage characteristics of ultrathin gate oxides after soft breakdown

Abstract: The current–voltage characteristics of metal-oxide-semiconductor capacitors with a 42 nm SiO2 gate oxide are investigated After the occurrence of soft breakdown, which is observed during constant current stress of the devices, the gate current is shown to behave like a power law of the applied gate voltage We propose that this power law behavior is due to the formation of a percolation path between the electrons traps generated in the SiO2 layer during current stress of the capacitor We describe a simple model which accounts for the current–voltage characteristics between two neighbor trapping sites, as well as a distribution of percolation thresholds in these (finite size) ultrathin SiO2 layers The prediction of the model is in fair agreement with the experimental results in a large voltage range, and leads to a better description of the data than previously reported models Furthermore, it is shown that this percolation model can also explain the temperature dependence of the gate current after the

Complementary metal gates and a process for implementation

Abstract: A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

Abstract: A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 /spl mu/m technologies.

Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy

Abstract: Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self-aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.

MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance

Abstract: A MOSgated trench type power semiconductor device is formed in 4H silicon carbide with the low resistivity direction of the silicon carbide being the direction of current flow in the device drift region. A P type diffusion at the bottom of the U shaped grooves in N− silicon carbide helps prevent breakdown of the gate oxide at the trench bottom edges. The gate oxide may be shaped to increase its thickness at the bottom edges and has a trapezoidal or spherical curvature. The devices may be implemented as depletion mode devices.

MISFET semiconductor device having relative impurity concentration levels between layers

Abstract: A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n + -type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n − -type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.