Showing papers on "Gate oxide published in 2000"

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

High breakdown GaN HEMT with overlapping gate structure

Abstract: GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 /spl mu/m. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm.

Low-voltage, 30 nm channel length, organic transistors with a self-assembled monolayer as gate insulating films

Abstract: We made nanometer-scale (gate length of 30 nm) organic thin-film transistors using a self-assembled monolayer (2 nm thick) as a gate insulator. The fabrication steps combine electron-beam lithography and lift-off techniques for the deposition of both metal electrodes and organic semiconductors with a chemical approach (self-assembly of organic molecules) to fabricate the gate insulator. Good performances of these transistors (with a record subthreshold slop of 350 mV/decade and a cutoff frequency of 20 kHz) and low-voltage operation (<2 V) are demonstrated down to a gate length of 200 nm. A gate voltage modulation of the source-to-drain tunnel current is demonstrated for the 30 nm gate length device.

Field effect transistors with SrTiO3 gate dielectric on Si

Abstract: SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si The capacitance of this 110 A dielectric film is electrically equivalent to less than 10 A of SiO2 This structure has been used to make capacitors and metal oxide semiconductor field effect transistors The interface trap density between the SrTiO3 and the Si is 64×1010 states/cm2 eV and the inversion layer mobility is 221 and 62 cm2/V s for n- and p-channel devices, respectively The gate leakage in these devices is two orders of magnitude smaller than a similar SiO2 gate dielectric field effect transistor

Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability

Abstract: The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible.

Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer

Abstract: A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region. Removal of unwanted regions of metal, and of in situ polysilicon, result in the definition of a metal gate structure, on the high k gate insulator layer, in the NMOS region, and in the definition of a metal—in situ doped polysilicon gate structure, on the high k gate insulator layer, in the PMOS region, with both gate structures embedded in openings in the composite insulator layer, previously formed via removal of the silicon nitride dummy gate structures.

Method for forming a patterned semiconductor film

Abstract: A process for forming a pattern in a semiconductor film is provided. The process comprises the steps of: providing a substrate; providing an organic semiconductor film adjacent the substrate; and providing a destructive agent adjacent selected portions of the organic semiconductor film, the destructive agent changing a property of selected portions of the organic semiconductor film substantially through the full thickness of the organic semiconductor film such that the property of the selected portions of the organic semiconductor film differs from the property of remaining portions of the organic semiconductor film. A method for manufacturing a transistor comprises the steps of: providing a substrate; providing a gate electrode adjacent the substrate; providing a gate dielectric adjacent the substrate and the gate electrode; providing a source electrode and a drain electrode adjacent the gate dielectric; providing a mask adjacent the gate dielectric in a pattern such that the source electrode, the drain electrode, and a portion of the gate dielectric remain exposed; and providing a semiconductor layer comprising one of an organic semiconductor and a plurality of inorganic colloidal particles, adjacent the source electrode, the drain electrode, the portion of the gate dielectric and the mask, thereby forming the transistor, the semiconductor layer having a thickness less than a thickness of the mask.

Method of forming dual metal gate structures for CMOS devices

Abstract: An embodiment of the instant invention is a method of forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate, the method comprising the steps of: forming a conductive material (step 216 of FIGURE 2) insulatively disposed over the semiconductor substrate, the conductive material having a work function; and altering a portion of the conductive material (step 218 of FIGURE 2) so as to change the work function of the altered conductive material, the conductive material to form the first gate electrode and the altered conductive material to form the second gate electrode. Preferably, the first transistor is an NMOS device, the second transistor is a PMOS device, and the first transistor and the second transistor form a CMOS device. The conductive material is, preferably, comprised of a conductor selected from the group consisting of: Ta, Mo, Ti and any combination thereof. Preferably, the step of altering a portion of the conductive material is comprised of: subjecting the portion of the conductive material to a plasma which incorporates a nitrogen-containing gas.

BSIM4 gate leakage model including source-drain partition

Abstract: Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

Ultrathin-body SOI MOSFET for deep-sub-tenth micron era

Abstract: A 40-nm-gate-length ultrathin-body (UTB) nMOSFET is presented with 20-nm body thickness and 2.4-nm gate oxide. The UTB structure eliminates leakage paths and is an extension of a conventional SOI MOSFET for deep-sub-tenth micron CMOS. Simulation shows that the UTB SOI MOSFET can be scaled down to 18-nm gate length with <5 nm UTB. A raised poly-Si S/D process is employed to reduce the parasitic series resistance.

Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures

Abstract: The charge retention characteristics in scaled SONOS nonvolatile memory devices with an effective gate oxide thickness of 94 A and a tunnel oxide of 15 A are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.

Gate leakage current mechanisms in AlGaN/GaN heterostructure field-effect transistors

Abstract: Gate leakage currents in AlGaN/GaN heterostructure field-effect transistor (HFET) structures with conventional and polarization-enhanced barriers have been studied Comparisons of extensive gate leakage current measurements with two-dimensional simulations show that vertical tunneling is the dominant mechanism for gate leakage current in the standard-barrier HFET and that the enhanced-barrier structure suppresses this mechanism in order to achieve a reduced leakage current An analytical model of vertical tunneling in a reverse-biased HFET gate-drain diode is developed to evaluate the plausibility of this conclusion The model can be fit to the measured data, but suggests that additional leakage mechanisms such as lateral tunneling from the edge of the gate to the drain or defect-assisted tunneling also contribute to the total leakage current The vertical tunneling current mechanism is shown to be more significant to the gate leakage current in III–V nitride HFETs than in HFETs fabricated in other III–V

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Abstract: Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

Gate length scaling and threshold voltage control of double-gate MOSFETs

Abstract: In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between the body and drain. Lateral S/D doping abruptness requirements for gate length scaling are examined. V/sub T/ control will be challenging as a single gate material for both NMOS and PMOS devices cannot provide low yet symmetrical V/sub T/'s. CMOS integration will thus require dual gate workfunction tuning, channel doping, or asymmetrical double-gates to adjust V/sub T/. Advantages of using alternative channel materials to facilitate scaling are investigated.

Process for making semiconductor device with epitaxially grown source and drain

Abstract: A method for making a semiconductor device. In that method, source and drain regions are epitaxially grown on a first part of a substrate. After a gate oxide is formed on a second part of the substrate, an etched polysilicon layer is formed on the gate oxide.

Electrical and reliability characteristics of ZrO2 deposited directly on Si for gate dielectric application

Abstract: ZrO2 thin film has been studied as an alternative gate dielectric. It was deposited directly on a Si substrate by reactive sputtering. An equivalent oxide thickness of less than 11 A with a leakage current of 1.9×10−3 A/cm2 at −1.5 V relative to the flat band voltage has been obtained. Well-behaved capacitance–voltage characteristics with an interface state density of less than 1011 cm−2 eV−1 and no significant frequency dispersion have been achieved. Excellent reliability properties (e.g., low charge trapping rate, good time-dependent dielectric breakdown, low stress-induced leakage current, and high dielectric breakdown) have also been obtained.

Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

Abstract: We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

Abstract: We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.

Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device

Abstract: A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain regions (13-14, 316-318, 321-323). A gate section (21) projects upwardly from between an adjacent pair of these regions, into an insulating layer (46, 363). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (51), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (56-57) on opposite sides of and immediately adjacent the gate section. A conductive layer (61, 120) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections. The portion of the conductive material remaining in each recess is self-aligned to be immediately adjacent at least one gate section, and serves as a local interconnect for a respective source or drain region.

Ultra-thin oxide reliability for ULSI applications

Abstract: In this article, we critically examine the limit of gate oxide scaling from a reliability point of view. The thickness dependence of the characteristic breakdown time (charge) and Weibull slope as well as the temperature dependence of oxide breakdown are measured with emphasis on accuracy. The failure modes of soft and hard breakdown events and their impact on device characteristics are reviewed. Using a two-dimensional reliability analysis, we explore the relative importance of characteristic breakdown time and Weibull slope in lifetime projection, and the possibilities of extending gate oxide beyond the currently predicted limit.

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e.g., a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

Modeling of 10-nm-scale ballistic MOSFET's

Abstract: We have performed numerical modeling of nanoscale dual-gate ballistic n-MOSFET's with ultrathin undoped channel, taking into account the effects of quantum tunneling along the channel and through the gate oxide. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the sub-10-nm devices potentially suitable for logic and memory applications, though their parameters are rather sensitive to size variations.

Memory device that includes passivated nanoclusters and method for manufacture

Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters ( 21 ) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate ( 12 ) upon which a tunnel dielectric layer ( 14 ) is formed. A plurality of nanoclusters ( 19 ) is then grown on the tunnel dielectric layer ( 14 ). After growth of the nanoclusters ( 21 ), a control dielectric layer ( 20 ) is formed over the nanoclusters ( 21 ). In order to prevent oxidation of the formed nanoclusters ( 21 ), the nanoclusters ( 21 ) may be encapsulated using various techniques prior to formation of the control dielectric layer ( 20 ). A gate electrode ( 24 ) is then formed over the control dielectric ( 20 ), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers ( 35 ), source and drain regions ( 32, 34 ) are then formed by implantation in the semiconductor layer ( 12 ) such that a channel region is formed between the source and drain regions ( 32, 34 ) underlying the gate electrode ( 24 ).

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

Abstract: Planar CMOS transistors have been fabricated to evaluate the 70 nm technology node using conventional transistor design methodologies Conventional CMOS transistors with 30 nm physical gate length were fabricated using aggressively scaled junctions, polysilicon gate electrode, gate oxide and Ni silicide These devices have inversion Cox exceeding 19 /spl mu/F/cm2, n-MOS gate delay (CV/I) of 094 ps and p-MOS gate delay of 17 ps at V/sub cc/=085 V These are the smallest CV/I values ever reported for Si CMOS devices The transistors also show good short channel control and subthreshold swings The n-MOS and p-MOS have drive currents equal to 514 /spl mu/A//spl mu/m and 285 /spl mu/A//spl mu/m respectively with I/sub off/ at or below 100 nA//spl mu/m at Vcc=085 V The saturation gm is equal to 1200 mS/mm for n-MOS and 640 mS/mm for p-MOS These are among the highest gm values ever reported The junction edge leakage is reasonably low with less than 1 nA//spl mu/m at 10 V and 100 C for both n-MOS and p-MOS These encouraging results suggest that the 70 nm technology node is achievable using conventional planar transistor design and process flow

Thin-film field-effect transistor with organic-inorganic hybrid semiconductor requiring low operating voltages

Abstract: A thin film transistor (TFT) device structure based on an organic-inorganic hybrid semiconductor material, that exhibits a high field effect mobility, high current modulation at lower operating voltages than the current state of the art organic-inorganic hybrid TFT devices. The structure comprises a suitable substrate disposed with the following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic-inorganic hybrid semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the gate voltage dependence of the organic-inorganic hybrid semiconductor to achieve high field effect mobility levels at very low operating voltages. Judicious combinations of the choice of this high dielectric constant gate insulator material and the means to integrate it into the organic-inorganic hybrid based TFT structure are taught that would enable easy fabrication on glass or plastic substrates and the use of such devices in flat panel display applications.

Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/μm or below) and a channel length (sub-lithographic, e.g., 0.1 μm or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Nonvolatile semiconductor memory device and method of operation thereof

Abstract: A MONOS type memory transistor increased in injection efficiency or storing a plurality of bits of data by local injection of a charge into part of a plane area of distribution of a charge storing means, comprised of a channel forming region of a first conductivity type, source and drain regions of a second conductivity type, gate insulating films formed on the channel forming region, gate electrodes, and a charge storing means (charge traps) formed in the gate insulating film and dispersed in a plane facing the channel forming region and the thickness direction and in which hot electrons caused by a band-to-band tunneling current are injected from the source and drain regions, where in the gate insulating film, between a first storage region and a second storage region into which electrons are locally injected, there is a third region into which hot electrons are not injected.

Field acceleration for oxide breakdown-can an accurate anode hole injection model resolve the E vs. 1/E controversy?

Abstract: A simple model, based on the concept of Anode Hole Injection, explains a number of puzzling measurements of oxide lifetime as a function of applied voltage. We provide systematic explanations of these measurements, and explore its implications for gate oxide reliability.

Local transport and trapping issues in Al2O3 gate oxide structures

Abstract: The bias dependence of interfacial barriers in Al2O3-based metal–oxide–semiconductor structures was studied by ballistic electron emission spectroscopy. Strong image force reductions of the barriers were observed. A conduction band offset between Al2O3 and Si of 2.78 eV was obtained. Electron trapping into levels that overlap the Si band gap and are located near the Si–Al2O3 interface led to charge densities of ∼2.5×1012 cm−2.