Showing papers on "Gate oxide published in 2001"

Graded thin films

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Limits on Silicon Nanoelectronics for Terascale Integration

Abstract: Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling

Abstract: A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N/sup +/, P/sup +/, Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-gate poly-Si/sub 1-x/Ge/sub x/-gated (x=0 or 0.25) CMOS devices for various gate oxide thicknesses. In addition, this model ran also be employed to determine the physical oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current).

Contact resistance in organic thin film transistors

Abstract: We present an analysis of the electrical characteristics of pentacene OTFTs fabricated on flexible polyethylene naphthalate (PEN) film. Nickel, silicon dioxide, and palladium were deposited by ion-beam sputtering and patterned by photolithography and lift-off to form the gate electrodes, the gate dielectric layer, and the source and drain contacts, respectively. An octadecyltrichlorosilane vapor prime was used to prepare the SiO/sub 2/ gate dielectric surface for the deposition of the pentacene layer, which was deposited by thermal evaporation and patterned using a water-soluble, photo-patterned polyvinyl alcohol layer.

Pi-Gate SOI MOSFET

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET.

Properties of high κ gate dielectrics Gd2O3 and Y2O3 for Si

Abstract: We present the materials growth and properties of both epitaxial and amorphous films of Gd2O3 (κ=14) and Y2O3 (κ=18) as the alternative gate dielectrics for Si. The rare earth oxide films were prepared by ultrahigh vacuum vapor deposition from an oxide source. The use of vicinal Si (100) substrates is key to the growth of (110) oriented, single domain films in the Mn2O3 structure. Compared to SiO2 gate oxide, the crystalline Gd2O3 and Y2O3 oxide films show a reduction of electrical leakage at 1 V by four orders of magnitude over an equivalent oxide thickness range of 10–20 A. The leakage of amorphous Y2O3 films is about six orders of magnitude better than SiO2 due to a smooth morphology and abrupt interface with Si. The absence of SiO2 segregation at the dielectric/Si interface is established from infrared absorption spectroscopy and scanning transmission electron microscopy. The amorphous Gd2O3 and Y2O3 films withstand the high temperature anneals to 850 °C and remain electrically and chemically intact.

Method of forming a double gate transistor having an epitaxial silicon/germanium channel region

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Effects of nitridation in gate oxides grown on 4H-SiC

Abstract: Experiments have demonstrated that nitridation provides critically important improvements in the quality of SiO2–SiC interface. This article provides results and analysis aimed at developing the much needed understanding of the mechanisms and effects associated with both annealing of pregrown oxides and direct growth in NO and N2O environments. According to the model proposed in the article, nitridation plays a double role: (1) creation of strong Si≡N bonds that passivate interface traps due to dangling and strained bonds, and (2) removal of carbon and associated complex silicon–oxycarbon bonds from the interface. This understanding of the effects of nitridation is experimentally verified and used to design a superior process for gate oxide growth in the industry-preferred N2O environment.

Method of forming graded thin films using alternating pulses of vapor phase reactants

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO 2 ) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

Abstract: Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10−5 A/cm2 at a bias of −1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ∼3×1011 states/cm eV wa...

Multi-layered gate for a CMOS imager

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Gate stack for high performance sub-micron CMOS devices

Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Annealing of high-k dielectric materials

Abstract: A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

Method of manufacturing a substrate using an SiGe layer

Abstract: A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Abstract: The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

Dual work function metal gate CMOS technology using metal interdiffusion

Abstract: In this letter, we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve low threshold voltages for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not disturb the delicate thin gate dielectric and preserves its uniformity and integrity. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

Silicon carbide semiconductor device and manufacturing method thereof

Abstract: In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n - -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

Abstract: N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 /spl mu/A//spl mu/m (or 1 mA//spl mu/m, depending on the definition of the width of the double-gate device) for V/sub g/-V/sub t/=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness.

Fin field effect transistor with self-aligned gate

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Structure and method for dual gate oxide thicknesses

Abstract: Structures and methods involving at least a pair of gate oxides having different thicknesses, one suitable for use in a logic device and one suitable for use in a memory device, have been shown. The method provided by the present invention affords a technique for ultra thin dual gate oxides having different thicknesses using a low temperature process in which no etching steps are required. The method includes forming a pair of gate oxides to a first thickness, which in one embodiment, includes a thickness of less than 5 nanometers. In one embodiment, forming the pair of gate oxides includes using a low-temperature oxidation method. A thin dielectric layer is then formed on one of the pair of gate oxides which is to remain as a thin gate oxide region for a transistor for use in a logic device. The thin dielectric layer exhibits a high resistance to oxidation at high temperatures. In one embodiment, the thin dielectric layer includes a thin dielectric layer of silicon nitride (Si3N4) formed using jet vapor deposition (JVD). The other of the pair of gate oxides is then formed to a second thickness to serve as a thick gate oxide region for a transistor for use in a memory device. Another embodiment of the present invention includes the structure of a logic device and a memory device formed on a single substrate as well as systems formed according to the method described above. In one embodiment, a dielectric layer of the transistor for use in the logic device has a thickness of less than 7 nanometers and a dielectric layer in the transistor for use in the memory device has a thickness of less than 12 nanometers.

Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device

Abstract: To improve a shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15 b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15 b) of the gate electrode 15G.

Impact of gate direct tunneling current on circuit performance: a simulation study

Abstract: The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.

Patterning organic–inorganic thin-film transistors using microcontact printed templates

Abstract: We report the simple, low-cost, and parallel fabrication of patterned organic–inorganic thin-film transistors (TFTs) by microcontact printing a molecular template on the substrate surface prior to film deposition. We printed molecules with hydrophobic tail groups on the gate oxide surfaces of TFTs to chemically, differentiate the substrate surface and confine the self-assembly of thin films, deposited from solutions flooded across the entire surface, to the transistor channels. TFTs are fabricated with good device characteristics and no current leakage. This process is more general to the patterning of other solution-deposited thin-film materials.

Method of forming a metal gate in a semiconductor device

Abstract: A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

Semiconductor device cell having regularly sized and arranged features

Abstract: In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.

Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits

Abstract: This paper reviews the physics and statistics of dielectric wearout and breakdown in ultra thin SiO/sub 2/-based CMOS gate dielectrics. Electrons or holes tunneling through gate oxide generate defects until a critical density is reached and the oxide breaks down. Critical defect density is explained by defect percolation path formation across the oxide; <1% of these paths lead to destructive breakdown, and the microscopic nature of the defects is not known. Defect generation rate decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron induced hydrogen release, but tunnel current increases exponentially with decreasing oxide thickness, giving decreasing time-to-breakdown and a lower reliability margin as device dimensions are scaled. Estimating dielectric reliability requires extrapolation from measurement conditions to operational conditions. Due to the lower reliability margin, it is imperative to reduce extrapolation error. Long term stress experiments are used to measure ultra thin dielectric film wearout and breakdown as close as possible to operating conditions, and have revealed the voltage dependence of the defect generation rate and critical defect density, allowing better time-to-breakdown voltage dependence modeling. Such measurements are used to guide pre-manufacturing technology development. We discuss electrical conduction through a breakdown spot, and the effect of oxide breakdown on device and circuit performance. In some cases, oxide breakdown does not lead to immediate circuit failure, and a quantitative methodology to predict circuit reliability must be developed.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Abstract: We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Highly reliable amorphous high-K gate oxide ZrO2

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.