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Showing papers on "Gate oxide published in 2003"


Journal ArticleDOI
23 May 2003-Science
TL;DR: The fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator provides a step toward the realization of transparent electronics for next-generation optoelectronics.
Abstract: We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO 3 (ZnO) 5 , as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of ∼10 6 and a field-effect mobility of ∼80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

2,724 citations


Patent
24 Jun 2003
TL;DR: In this article, a gate electrode is formed on the gate insulating layer, and a source contact and a drain contact are disposed at the both sides of the gate contact and are electrically connected to the channel layer via openings.
Abstract: A zinc oxide (ZnO) field effect transistor exhibits large input amplitude by using a gate insulating layer. A channel layer and the gate insulating layer are sequentially laminated on a substrate. A gate electrode is formed on the gate insulating layer. A source contact and a drain contact are disposed at the both sides of the gate contact and are electrically connected to the channel layer via openings. The channel layer is formed from n-type ZnO. The gate insulating layer is made from aluminum nitride/aluminum gallium nitride (AlN/AlGaN) or magnesium zinc oxide (MgZnO), which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a silicon metal oxide semiconductor field effect transistor (Si-MOS-type FET), resulting in the formation of an inversion layer.

1,048 citations


Proceedings ArticleDOI
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

729 citations


Patent
22 Aug 2003
TL;DR: In this paper, a gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the SINR, which is a semiconductor device consisting of a top surface and laterally-opposite sidewalls formed on a substrate.
Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

559 citations


Journal ArticleDOI
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.
Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

505 citations


Patent
24 Jun 2003
TL;DR: In this article, the dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide, where the layer of the hafium oxide is adjacent and in contact with the surface of the lanthanides.
Abstract: Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 . Forming a layer of hafnium oxide by atomic layer deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

304 citations


Journal ArticleDOI
TL;DR: In this paper, a GaAs MOSFET with thin Al2O3 gate dielectric in nanometer (nm) range grown by atomic layer deposition is demonstrated, which shows a good linearity, low gate leakage current, and negligible hysteresis in drain current in a wide range of bias voltage.
Abstract: A GaAs metal–oxide–semiconductor field-effect transistor (MOSFET) with thin Al2O3 gate dielectric in nanometer (nm) range grown by atomic layer deposition is demonstrated. The nm-thin oxide layer with significant gate leakage current suppression is one of the key factors in downsizing field-effect transistors. A 1 μm gate-length depletion-mode n-channel GaAs MOSFET with an Al2O3 gate oxide thickness of 8 nm, an equivalent SiO2 thickness of ∼3 nm, shows a broad maximum transconductance of 120 mS/mm and a drain current of more than 400 mA/mm. The device shows a good linearity, low gate leakage current, and negligible hysteresis in drain current in a wide range of bias voltage.

300 citations


Journal ArticleDOI
TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.
Abstract: Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

285 citations


Patent
05 May 2003
TL;DR: In this paper, an ALD-based method was proposed for high performance MOS devices and transistor gate stacks. But it is not suitable for the use of high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in processing steps subsequent to the deposition of the gate dielectric layer of the device.
Abstract: A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode. Furthermore, the barrier film prevents the electrode material from reacting with the gate dielectric material. The barrier layer is ultra thin and, at the same time, it forms a uniform cover over the entire surface of the gate dielectric.

285 citations


Proceedings ArticleDOI
08 Dec 2003
TL;DR: In this paper, a novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFETs on (100) surface) through wafer bonding and selective epitaxy devices with physical gate oxide thickness of 12 nm.
Abstract: A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy CMOS devices with physical gate oxide thickness of 12 nm have been demonstrated, with substantial enhancement of pFET drive current at L/sub poly//spl les/80 nm

284 citations


Patent
Scott Hareland1, Robert S. Chau1, Brian S. Doyle1, Rafael Rios1, Tom Linton1, Suman Datta1 
15 Dec 2003
TL;DR: In this paper, a nonplanar semiconductor device and its method of fabrication is described, which includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate.
Abstract: A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Journal ArticleDOI
Evgeni Gusev1, Cyril Cabral1, Matthew Copel1, Christopher P. D'Emic1, Michael A. Gribelyuk1 
TL;DR: In this paper, growth behavior, structure, thermal stability and electrical properties of ultrathin hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl4 and H2O at 300°C on a bare silicon surface or a thin thermally grown SiO2-based interlayer.

Patent
19 Feb 2003
TL;DR: In this article, a self-aligned carbon-nanotube field effect transistor semiconductor device is described, which consists of a carbon-notube, a source and a drain, and a gate.
Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from 10 the carbon-nanotube by a dielectric film [111].

Journal ArticleDOI
TL;DR: In this article, the gate dielectric grown by atomic layer deposition (ALD) was demonstrated for the first time on a III-V compound semiconductor MOSFET.
Abstract: For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.

Journal ArticleDOI
TL;DR: In this article, a compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs is derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included.
Abstract: A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.

Patent
19 Mar 2003
TL;DR: In this paper, a method and structure for a transistor that includes an insulator and a silicon structure on the insulator is presented, where a first gate is positioned on a first side of the central portion of the silicon structure.
Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

Patent
Scott Hareland1, Robert S. Chau1, Brian S. Doyle1, Suman Datta1, Been-Yih Jin1 
12 Dec 2003
TL;DR: In this paper, a semiconductor device consisting of a top surface and laterally opposite sidewalls is formed on an insulating substrate, where a gate dielectric layer is created on the top surface of the semiconductor body.
Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

Journal ArticleDOI
TL;DR: It is found that the current through the bulk portion is independent of gate length for any gate voltage, offering direct evidence for ballistic transport in semiconducting carbon nanotubes over at least a few hundred nanometers, even for relatively small carrier velocities.
Abstract: We have fabricated carbon-nanotube (CN) field-effect transistors with multiple, individually addressable gate segments. The devices exhibit markedly different transistor characteristics when switched using gate segments controlling the device interior versus those near the source and drain. We ascribe this difference to a change from Schottky-barrier modulation at the contacts to bulk switching. We also find that the current through the bulk portion is independent of gate length for any gate voltage, offering direct evidence for ballistic transport in semiconducting carbon nanotubes over at least a few hundred nanometers, even for relatively small carrier velocities.

Patent
07 Feb 2003
TL;DR: In this paper, a gate dielectric and a gate are provided respectively on and over a semiconductor substrate, and an integrated circuit, and manufacturing method therefor, is provided, where a junction is formed adjacent the gate, and a shaped spacer is formed around the gate.
Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Journal ArticleDOI
TL;DR: In this article, germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer are presented.
Abstract: In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.

Patent
25 Mar 2003
TL;DR: In this article, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric, and an oxygen diffusion barrier is then formed on the sidewalls of the gate, to prevent oxygen from diffusing laterally into the oxygen permeability gate.
Abstract: A method and apparatus of preventing lateral oxidation through gate dielectrics that are highly permeable to oxygen diffusion, such as high-k gate dielectrics. According to one embodiment of the invention, a gate structure is formed on a substrate, the gate structure having an oxygen-permeable gate dielectric. An oxygen diffusion barrier is then formed on the sidewalls of the gate structure to prevent oxygen from diffusing laterally into the oxygen-permeable gate dielectric, thus preventing oxidation to the substrate underneath the gate dielectric or to the electrically conductive gate electrode overlying the gate dielectric.

Patent
20 Feb 2003
TL;DR: In this paper, a gate dielectric and a gate electrode both wrap around the nano-rod structure to form a transistor device, and the gate is then used as a gate channel.
Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Patent
09 Sep 2003
TL;DR: In this article, a flash memory cell and a method of forming the same are described, where the flash cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element.
Abstract: A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

Journal ArticleDOI
TL;DR: A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit.
Abstract: In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.

Journal ArticleDOI
TL;DR: In this article, the authors show that carbon nanotube Schottky-barrier transistors exhibit scaling that is qualitatively different than conventional transistors, which depends in an unexpected way on both the thickness and the dielectric constant of the gate oxide.
Abstract: We show that carbon nanotube Schottky-barrier transistors exhibit scaling that is qualitatively different than conventional transistors The performance depends in an unexpected way on both the thickness and the dielectric constant of the gate oxide Experimental measurements and theoretical calculations for ambipolar devices provide a consistent understanding of the novel scaling, which reflects the very different device physics of a Schottky-barrier transistor with a quasi-one-dimensional channel contacting a sharp edge A simple analytic model gives explicit scaling expressions for key device parameters such as subthreshold slope, turn-on voltage, and transconductance

Patent
Akihisa Yamaguchi1
27 Jan 2003
TL;DR: In this paper, a reduction of leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device by forming a silicon oxide film and a silicon nitride film on a substrate, which is then heated to a temperature within a range of 20°C-600°C.
Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.-600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.

Patent
14 Jan 2003
TL;DR: In this paper, the Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2.
Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2 . The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

Patent
14 Aug 2003
TL;DR: In this paper, a low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug to reduce the parasitic capacitance, thus, higher density of devices can be formed without decreasing operating speed.
Abstract: A semiconductor device with a low-k material in close proximity thereto and its fabrication method. The device includes a gate electrode overlying a substrate. An electrically conductive plug is provided immediately adjacent to the gate electrode and making electrical contact to the device. A low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug whereby reducing the parasitic capacitance. Thus, higher density of devices can be formed without decreasing operating speed.

Patent
13 Nov 2003
TL;DR: In this article, a semiconductor device is provided to avoid a defect of a gate oxide layer and solve a scratch problem by depositing an oxide layer of a thickness corresponding to the depth of a trench and selectively etching the oxide layer to form a trench oxide layer.
Abstract: PURPOSE: A semiconductor device is provided to avoid a defect of a gate oxide layer and solve a scratch problem by depositing an oxide layer of a thickness corresponding to the depth of a trench and by selectively etching the oxide layer to form a trench oxide layer. CONSTITUTION: An oxide layer that has a thickness corresponding to a desired depth of the trench and a width corresponding to a desired width of the trench is patterned on a silicon wafer(11). A shallow silicon epitaxial layer(13) thinner than the oxide layer is formed between the patterned oxide layers and on the silicon wafer. A gate oxide layer(14) of a predetermined width is formed on the silicon epitaxial layer. A gate(15) is formed on the gate oxide layer. An impurity-doped LDD(lightly doped drain) region(16) is formed in the outside of the gate and in the silicon epitaxial layer. Sidewalls(17) are formed on the sides of the oxide layer and the gate formed on the silicon epitaxial layer. An impurity-doped source/drain region(18) is formed in the silicon epitaxial layer deeper than the LDD region in the outside of the sidewall.

Proceedings ArticleDOI
14 Apr 2003
TL;DR: In this paper, a power trench MOSFET with W-shaped gate structure is presented, which demonstrates a significant reduction in gate-drain charge Qgd, a low on-resistance, and good production process margin.
Abstract: A new power Trench MOSFET with W-shaped gate structure (WMOSFET) that demonstrates a significant reduction in gate-drain charge Qgd, a low on-resistance, and good production process margin is reported. The gate is formed using a thicker oxide at the bottom of the trench that is self-aligned to the P-body/N-epi junction. Fabricated 35 V N-channel devices exhibit a Rdson*Qgd Figure of Merit of 12.5 m/spl Omega/.nC with V/sub GS/=10V and V/sub DD/=15V. Experimental data of devices fabricated using LOCOS and Sub Atmospheric CVD (SACVD) processes to form the thicker oxide layer along with simulation results are presented.