Showing papers on "Gate oxide published in 2005"

Amorphous oxide and thin film transistor

Abstract: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 10 18 /cm 3 , and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6 , a drain electrode 5 , a gate electrode 4 , a gate insulating film 3 , and a channel layer 2 , an amorphous oxide having an electron carrier concentration less than 10 18 /cm 3 is used in the channel layer 2.

High-performance carbon nanotube field-effect transistor with tunable polarities

Abstract: State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky-barrier-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance enhancement-mode CNFETs exhibiting n- or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S=63 mV/dec). The device design allows for aggressive oxide thickness and gate-length scaling while maintaining the desired device characteristics.

GaN metal-oxide-semiconductor high-electron-mobility-transistor with atomic layer deposited Al2O3 as gate dielectric

Abstract: We report on a GaN metal-oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) using atomic-layer-deposited (ALD) Al2O3 as the gate dielectric. Compared to a conventional GaN high-electron-mobility-transistor (HEMT) of similar design, the MOS-HEMT exhibits several orders of magnitude lower gate leakage and several times higher breakdown voltage and channel current. This implies that the ALD Al2O3∕AlGaN interface is of high quality and the ALD Al2O3∕AlGaN∕GaN MOS-HEMT is of high potential for high-power rf applications. In addition, the high-quality ALD Al2O3 gate dielectric allows the effective two-dimensional (2D) electron mobility at the AlGaN∕GaN heterojunction to be measured under a high transverse field. The resulting effective 2D electron mobility is much higher than that typical of Si, GaAs or InGaAs metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Defect energy levels in HfO2 high-dielectric-constant gate oxide

Abstract: This letter presents calculations of the energy levels of the oxygen vacancy and oxygen interstitial defects in HfO2 using density functional methods that do not need an empirical band gap correction The levels are aligned to those of the Si channel using the known band offsets The oxygen vacancy gives an energy level nearer the HfO2 conduction band and just above the Si gap, depending on its charge state It is identified as the main electron trap in HfO2 The oxygen interstitial gives levels just above the oxide valence band

ATOMIC LAYER DEPOSITION OF Zrx Hfy Sn1-x-y O2 FILMS AS HIGH k GATE DIELECTRICS

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) and tin oxide (SnO 2 ) acting as a single dielectric layer with a formula of Zr X Hf Y Sn 1-X-Y O 2 , and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.

Field effect transistor with amorphous oxide active layer containing microcrystals and gate electrode opposed to active layer through gate insulator

Abstract: A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals.

Low-voltage operation of a pentacene field-effect transistor with a polymer electrolyte gate dielectric

Abstract: Large operating voltages are often required to switch organic field-effect transistors (OFETs) on and off because commonly used gate dielectric layers provide low capacitive coupling between the gate electrode and the semiconductor. We present here a pentacene OFET gated by a solution-deposited polymer electrolyte film in which the current was modulated over four orders of magnitude using gate voltages less than 2V. A subthreshold slope of 180mV per decade of current was observed during transistor turn on at a source-drain bias of −1V; the estimated dielectric layer specific capacitance was 5μF∕cm2. Sweep rate-dependent hysteresis may be attributed to a combination of ion migration and charge carrier trapping effects. Strategies to improve switching speeds for polymer electrolyte-gated OFETs are also discussed.

Light emission from an ambipolar semiconducting polymer field-effect transistor

Abstract: Ambipolar light-emitting field-effect transistors are fabricated with two different metals for the top-contact source and drain electrodes; a low-work-function metal defining the channel for the source electrode and a high-work-function metal defining the channel for the drain electrode. A thin film of polypropylene-co-1-butene on SiNx is used as the gate dielectric on an n++-Si wafer, which functioned as the substrate and the gate electrode. Transport data show ambipolar behavior. Recombination of electrons and holes results in a narrow zone of light emission within the channel. The location of the emission zone is controlled by the gate bias.

Interfaces and defects of high-K oxides on silicon

Abstract: The properties of oxides with high-dielectric constant are being extensively studied for use as gate oxides. The criteria for choosing such oxides is discussed. The bonding at Si–oxide interfaces is considered in order to obtain an insulating interface. The stabilities of various atomic configurations of interface are compared, and their band offsets are calculated. The energy levels of point defects are calculated and the origin of fixed charge present is discussed.

Self-aligned contacts for transistors

Abstract: Self-aligned contacts for transistors and methods for fabricating the contacts are described. An etch resistant material is patterned to create an opening that resides above a transistor gate structure. A selective etch is performed through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor. Conductive material is deposited that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source region of the diffusion layer of the transistor. A layer above the conductive material is formed. Contacts are formed through the layer above the conductive material to respective portions of the conductive material that cover respective tops of the drain and source regions of the diffusion layer of the transistor.

Process for manufacturing dual work function metal gates in a microelectronics device

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200 . In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315 a and 315 b . The nMOS and pMOS stacked gate structures 315 a and 315 b each comprise a gate dielectric 205 , a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305 . The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Electronic apparatus with deposited dielectric layers

Abstract: An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate surface by atomic layer deposition and depositing a hafnium oxide layer on the hafnium metal layer by atomic layer deposition form a hafnium oxide dielectric layer substantially free of silicon oxide. Dielectric layers containing atomic layer deposited hafnium oxide are thermodynamically stable such that the hafnium oxide will have minimal reactions with a silicon substrate or other structures during processing.

Non-volatile memory cell using high-k material and inter-gate programming

Abstract: A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

Manufacturing method of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device whereby the problem is solved that in a semiconductor device separated by a trench, a square is formed at the shoulder of STI which is the boundary between a separating region and an active region so that a gate oxide film becomes thinner locally at this shoulder, the reliability of the gate oxide film is degraded by the concentration of an electric field etc., or the performance of a transistor is degraded; and a highly reliable semiconductor device is manufactured by rounding the shoulder to eliminate the local thickness variation of the gate oxide film to improve the reliability thereof. SOLUTION: The heat treatment for rounding the square portion of the shoulder of the STI is carried out in a rare gas atmosphere for a long time at a high temperature not less than 1000°C. The shoulder is rounded, and the rare gas is used to eliminate the effect of nitrogen on a silicon interface. Thus, the local thickness variations of the gate oxide film can be eliminated to improve the reliability thereof. COPYRIGHT: (C)2006,JPO&NCIPI

Polymer electrolyte gate dielectric reveals finite windows of high conductivity in organic thin film transistors at high charge carrier densities.

Abstract: Finite regions of high conductivity were observed in both n- and p-channel organic thin film transistors based on polycrystalline organic semiconductor films and a solution-processed, solid polymer electrolyte gate dielectric The transition from a highly conductive state to a more insulating state with increasing gate bias may be attributed to the realization of carrier densities greater than 1014 charges/cm2 in the semiconductor film

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

Split-channel antifuse array architecture

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

Silicon carbide semiconductor device and method for manufacturing the same

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

Enhancement mode III-nitride FET

Abstract: A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.

Thin film semiconductor apparatus and method for driving the same

Abstract: A thin film semiconductor apparatus comprising thin film transistors integrated on a substrate, and a wiring connecting the thin film transistors to one another, wherein each of the thin film transistors comprises a channel which has a predetermined threshold-voltage and on-off operates depending on a gate voltage applied through a wiring, wherein at least a part of the thin film transistors comprises a semiconductor thin film constituting the channel, and a first gate electrode and a second gate electrode disposed on a surface and a back surface of the semiconductor thin film through an insulating film, wherein the first and second gate electrodes receive a first gate voltage and a second gate voltage, respectively, through wirings which are separately provided, wherein the first gate electrode on-off controls the channel depending on the first gate voltage, and wherein the second gate electrode actively controls the threshold voltage depending on the second gate voltage to render the on-off operation of the thin film transistors appropriate. The semiconductor apparatus of the present invention is advantageous in that the threshold voltage can be actively controlled in accordance with the-dispersion of the threshold voltage, so that an increase in consumed power, an erroneous operation and the like can be suppressed. Thus, it is possible to stably provide a high performance threshold voltage circuit array in high yield.

Asymmetric band-gap engineered nonvolatile memory device

Abstract: Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

Self DC-bias high frequency logic gate, high frequency NAND gate and high frequency NOR gate

Abstract: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics

Abstract: An accumulation-mode design for nanometer-scale electromechanical-gate field effect transistors (NEMFETs) is proposed and studied via simulation In the off state, the gate electrode is in contact with the thin gate dielectric and short-channel effects are effectively suppressed In the on state, the gate electrode is separated from the thin gate dielectric so that the threshold voltage VT is dynamically lowered and the transistor drive current I on is enhanced, and gate leakage is eliminated The NEMFET can likely meet performance specifications for low-power applications at 25 nm gate length, and is attractive for scaled supply voltage operation

Methods of fabricating nitride-based transistors with a cap layer and a recessed gate

Abstract: An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.

Silicon oxide cap over high dielectric constant films

Abstract: A method for forming an integrated circuit structure on a semiconductor substrate comprises depositing a high k gate dielectric material over the substrate using an atomic layer deposition process. A silicon oxide capping layer is deposited over the gate dielectric material in a rapid thermal chemical vapor deposition process. A gate electrode is formed over the silicon oxide capping layer.

ALD of amorphous lanthanide doped TiOx films

Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO x ) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.