Showing papers on "Gate oxide published in 2012"

Gallium oxide (Ga2O3) metal-semiconductor field-effect transistors on single-crystal β-Ga2O3 (010) substrates

Abstract: We report a demonstration of single-crystal gallium oxide (Ga2O3) metal-semiconductor field-effect transistors (MESFETs). A Sn-doped Ga2O3 layer was grown on a semi-insulating β-Ga2O3 (010) substrate by molecular-beam epitaxy. We fabricated a circular MESFET with a gate length of 4 μm and a source–drain spacing of 20 μm. The device showed an ideal transistor action represented by the drain current modulation due to the gate voltage (VGS) swing. A complete drain current pinch-off characteristic was also obtained for VGS < −20 V, and the three-terminal off-state breakdown voltage was over 250 V. A low drain leakage current of 3 μA at the off-state led to a high on/off drain current ratio of about 10 000. These device characteristics obtained at the early stage indicate the great potential of Ga2O3-based electrical devices for future power device applications.

Ultrahigh density vertical nand memory device and method of making thereof

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Nonvolatile memory device and method for fabricating the same

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

CMOS Process-Compatible High-Power Low-Leakage AlGaN/GaN MISHEMT on Silicon

Abstract: We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si3N4/Al2O3 bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance Ron, sp of 2.9 mΩ·cm2. The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

Vertical nand device with low capacitance and silicided word lines

Abstract: A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.

22-nm fully-depleted tri-gate CMOS transistors

Abstract: At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS The use of tri-gate transistors provides steep subthreshold slopes (∼70 mV/decade) and very low DIBL (∼50 mV/V) values that are critical for low voltage operation Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch This enables an SRAM cell size of 0092 μm2 High yield and reliability have been demonstrated on multiple microprocessors

Through-Substrate Vias and Methods for Forming the Same

Abstract: A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Integrated circuit with a thin body field effect transistor and capacitor

Abstract: A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.

Methods of atomic-layer deposition of hafnium oxide/erbium oxide bi-layer as advanced gate dielectrics

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Process for depositing electrode with high effective work function

Abstract: According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.

N metal for FinFET

Abstract: An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer.

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing on-resistance while preventing the occurrence of punch-through.SOLUTION: A MOSFET 1 comprises: a silicon carbide substrate 10, an active layer 20, a gate oxide film 30, and a gate electrode 40. The active layer 20 includes a body region 22 in which an inversion layer 29 is formed in the region contacting the gate oxide film 30 by applying a voltage to the gate electrode 40. The body region 22 has a low-concentration region 22B that is disposed in the region in which the inversion layer 29 is formed and contains an impurity having a low concentration, and a high-concentration region 22A that is adjacent to the low-concentration region 22B in the moving direction of carriers in the inversion layer 29, is disposed in the region in which the inversion layer 29 is formed, and contains an impurity having a higher concentration than that in the low-concentration region 22B.

CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric V t for the PMOS and NMOS FETs.

Finfet parasitic capacitance reduction using air gap

Abstract: Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

Abstract: We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Abstract: Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.

Control of efficiency, brightness, and recombination zone in light-emitting field effect transistors.

Abstract: The split-gate light emitting field effect transistors (SG-LEFETs) demonstrate a new strategy for ambipolar LEFETs to achieve high brightness and efficiency simultaneously. The SG architecture forces largest quantity of opposite charges on Gate 1 and Gate 2 area to meet in the center of the channel. By actively and independently controlling current injection from separated gate electrodes within transporting channel, high brightness can be obtained in the largest injection current regime with highest efficiency.

Graphene−Graphite Oxide Field-Effect Transistors

Abstract: Graphene’s high mobility and two-dimensional nature make it an attractive material for field-effect transistors. Previous efforts in this area have used bulk gate dielectric materials such as SiO2 or HfO2. In contrast, we have studied the use of an ultrathin layered material, graphene’s insulating analogue, graphite oxide. We have fabricated transistors comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. The graphite oxide layers show relatively minimal leakage at room temperature. The breakdown electric field of graphite oxide was found to be comparable to SiO2, typically ∼1–3 × 108 V/m, while its dielectric constant is slightly higher, κ ≈ 4.3.

Source/drain stack stressor for semiconductor device

Abstract: The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.

Replacement source/drain finfet fabrication

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

The role of charge traps in inducing hysteresis: capacitance - voltage measurements on top gated bilayer graphene

Abstract: Understanding the origin of hysteresis in the channel resistance from top gated graphene transistors is important for transistor applications. Capacitance - voltage measurements across the gate oxide on top gated bilayer graphene show hysteresis with a charging and discharging time constant of ~100 {\mu}s. However, the measured capacitance across the graphene channel does not show any hysteresis, but shows an abrupt jump at a high channel voltage due to the emergence of an order, indicating that the origin of hysteresis between gate and source is due to charge traps present in the gate oxide and graphene interface.

Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

Abstract: High permittivity (k) gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO2 and La2O3. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La2O3), are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

High voltage device

Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

Semiconductor device incorporating a multi-function layer into gate stacks

Abstract: Approaches are provided for forming a semiconductor device (e.g., a FET) having a multi-function layer (e.g., niobium carbide (NbC)) that serves as a work function layer and a gate metal layer in gate stacks of solid state applications. By introducing a single layer with multiple functions, total number of layers that needs processing (e.g., recessing) may be decreased. As such, the complexity of device integration and resulting complications may be reduced.

Double layer capacitance measured by organic field effect transistor operated in water

Abstract: Pentacene ultra thin film transistors were exposed to water and operated with a conventional silicon/silicon oxide bottom gate and an electrolyte top gate controlled by a working electrode. The transistors are highly sensible (µV) to the electrochemical potential of the aqueous electrolyte. We show that dual gate operation permits the measurement of the double layer capacitance, CDL = 14.6 µF/cm2. The device exhibits a fast (4.6 ms) and stable response, without bias stress as opposed to conventional bottom gate operations, when controlled with the electrolyte gate. These features make the device a promising candidate for potentiometric transducers required for non-invasive electrophysiology.

Studies on room-temperature electric-field effect in ionic-liquid gated VO 2 three-terminal devices

Abstract: We present a study of electrostatic gating of VO2 thin films in ionic-liquid-based electric double-layer transistor geometry. Devices were fabricated by lithographic patterning of VO2 thin films as channel on sapphire substrates, ionic liquid as gate dielectric, and Au as gate/source/drain electrode, respectively. A significant unipolar increase in channel conductance at room temperature is observed. The VO2 channel resistance decreases ∼50% at + 2 V gate bias, whereas it increases slightly under negative bias. The polarity dependence of resistance modulation suggests electrons to be a dominant carrier, which is consistent with Hall measurements. In the high-temperature metallic state of VO2, no gating effect is observed. The effect of multiple transition cycles on the channel resistance change under bias is discussed. The study contributes to on-going efforts to realize room-temperature field-effect switches with correlated oxides.

Aligned gate-all-around structure

Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

Borderless Contacts For Semiconductor Devices

Abstract: In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

True Reference Nanosensor Realized with Silicon Nanowires

Abstract: Conventional gate oxide layers (e.g., SiO2, Al2O3, or HfO2) in silicon field-effect transistors (FETs) provide highly active surfaces, which can be exploited for electronic pH sensing. Recently, great progress has been achieved in pH sensing using compact integrateable nanowire FETs. However, it has turned out to be much harder to realize a true reference electrode, which – while sensing the electrostatic potential – does not respond to the proton concentration. In this work, we demonstrate a highly effective reference sensor, a so-called reference FET, whose proton sensitivity is suppressed by as much as 2 orders of magnitude. To do so, the Al2O3 surface of a nanowire FET was passivated with a self-assembled monolayer of silanes with a long alkyl chain. We have found that a full passivation can be achieved only after an extended period of self-assembling lasting several days at 80 °C. We use this slow process to measure the number of active proton binding sites as a function of time by a quantitative com...

Methods of Forming Replacement Gate Structures for Semiconductor Devices

Abstract: Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal.