Showing papers on "Gate oxide published in 2014"

Tunable Transport Gap in Phosphorene

Abstract: In this article, we experimentally demonstrate that the transport gap of phosphorene can be tuned monotonically from ∼0.3 to ∼1.0 eV when the flake thickness is scaled down from bulk to a single layer. As a consequence, the ON current, the OFF current, and the current ON/OFF ratios of phosphorene field effect transistors (FETs) were found to be significantly impacted by the layer thickness. The transport gap was determined from the transfer characteristics of phosphorene FETs using a robust technique that has not been reported before. The detailed mathematical model is also provided. By scaling the thickness of the gate oxide, we were also able to demonstrate enhanced ambipolar conduction in monolayer and few layer phosphorene FETs. The asymmetry of the electron and the hole current was found to be dependent on the layer thickness that can be explained by dynamic changes of the metal Fermi level with the energy band of phosphorene depending on the layer number. We also extracted the Schottky barrier heigh...

Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

Abstract: In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as \(1 \times 10^{19}\) cm \(^{-3}\) .

Nanocrystalline cellulose applied simultaneously as the gate dielectric and the substrate in flexible field effect transistors

Abstract: Cotton-based nanocrystalline cellulose (NCC), also known as nanopaper, one of the major sources of renewable materials, is a promising substrate and component for producing low cost fully recyclable flexible paper electronic devices and systems due to its properties (lightweight, stiffness, non-toxicity, transparency, low thermal expansion, gas impermeability and improved mechanical properties). Here, we have demonstrated for the first time a thin transparent nanopaper-based field effect transistor (FET) where NCC is simultaneously used as the substrate and as the gate dielectric layer in an ‘interstrate’ structure, since the device is built on both sides of the NCC films; while the active channel layer is based on oxide amorphous semiconductors, the gate electrode is based on a transparent conductive oxide. Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility (>7 cm 2 V 1 s 1 ), drain‐source current on=off modulation ratio higher than 10 5 , enhancement n-type operation and subthreshold gate voltage swing of 2.11 V=decade. The NCC film FET characteristics have been measured in air ambient conditions and present good stability, after two weeks of being processed, without any type of encapsulation or passivation layer. The results obtained are comparable to ones produced for conventional cellulose paper, marking this out as a promising approach for attaining high-performance disposable electronics such as paper displays, smart labels, smart packaging, RFID (radio-frequency identification) and point-of-care systems for self-analysis in bioscience applications, among others.

A 1200-V, 60-A SiC MOSFET Multichip Phase-Leg Module for High-Temperature, High-Frequency Applications

Abstract: In this paper, a high-temperature, high-frequency, wire-bond-based multichip phase-leg module was designed, fabricated, and fully tested. Using paralleled Silicon Carbide (SiC) MOSFETs, the module was rated at 1200 V and 60 A, and was designed for a 25-kW three-phase inverter operating at a switching frequency of 70 kHz, and in a harsh environment up to 200 °C, for aircraft applications. To this end, the temperature-dependent characteristics of the SiC MOSFET were first evaluated. The results demonstrated the superiority of the SiC MOSFET in both static and switching performances compared to Si devices, but meanwhile did reveal the design tradeoff in terms of the device's gate oxide stability. Various high-temperature packaging materials were then extensively surveyed and carefully selected for the module to sustain the harsh environment. The electrical layout of the module was also optimized using a modeling and simulation approach, in order to minimize the device parasitic ringing during high-speed switching. Finally, the static and switching performances of the fabricated module were tested, and the 200 °C continuous operation of the SiC MOSFETs was verified.

C-H surface diamond field effect transistors for high temperature (400 °C) and high voltage (500 V) operation

Abstract: By forming a highly stable Al2O3 gate oxide on a C-H bonded channel of diamond, high-temperature, and high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) has been realized. From room temperature to 400 °C (673 K), the variation of maximum drain-current is within 30% at a given gate bias. The maximum breakdown voltage (VB) of the MOSFET without a field plate is 600 V at a gate-drain distance (LGD) of 7 μm. We fabricated some MOSFETs for which VB/LGD > 100 V/μm. These values are comparable to those of lateral SiC or GaN FETs. The Al2O3 was deposited on the C-H surface by atomic layer deposition (ALD) at 450 °C using H2O as an oxidant. The ALD at relatively high temperature results in stable p-type conduction and FET operation at 400 °C in vacuum. The drain current density and transconductance normalized by the gate width are almost constant from room temperature to 400 °C in vacuum and are about 10 times higher than those of boron-doped diamond FETs.

High photosensitivity few-layered MoSe2 back-gated field-effect phototransistors.

Abstract: In this paper, we report on the fabrication and optoelectronic properties of high sensitive phototransistors based on few-layered MoSe2 back-gated field-effect transistors, with a mobility of 19.7 cm2 V−1 s−1 at room temperature. We obtained an ultrahigh photoresponsivity of 97.1 AW−1 and an external quantum efficiency (EQE) of 22 666% using 532 nm laser excitation at room temperature. The photoresponsivity was improved near the threshold gate voltage; however, the selection of the silicon dioxide as a gate oxide represents a limiting factor in the ultimate performance. Thanks to their high photoresponsivity and external quantum efficiency, the few-layered MoSe2-based devices are promising for photoelectronic applications.

Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device

Abstract: A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.

Role of Ga vacancy on a multilayer GaTe phototransistor.

Abstract: We report a high-performance field-effect transistor (FET) and phototransistor based on back-gated multilayer GaTe nanosheets. Through both electrical transport measurements at variable temperatures and first-principles calculations, we find Ga ion vacancy is the critical factor that causes high off-state current, low on/off ratio, and large hysteresis of GaTe FET at room temperature. By suppressing thermally activated Ga vacancy defects at liquid nitrogen temperature, a GaTe nanosheet FET with on/off ratio of ∼105, off-state current of ∼10–12 A, and negligible gate hysteresis is successfully demonstrated. Furthermore, a GaTe phototransistor with high photogain above 2000 and high responsivity over 800 AW–1 is achieved, as well. Our findings are of scientific importance to understand the physical nature of intrinsic GaTe transistor performance degradation and also technical significance to unlock the hurdle for practical applications of GaTe transistors in the future.

Integrated circuits with varying gate structures and fabrication methods

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

A 2-D Analytical Model for Double-Gate Tunnel FETs

Abstract: This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.

Silicide protection during contact metallization and resulting semiconductor structures

Abstract: A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

High aspect ratio memory hole channel contact formation

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

Flash gate air gap

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Gate Oxide Degradation of SiC MOSFET in Switching Conditions

Abstract: Under realistic switching conditions, SiC MOSFETs reliability issues remain as a challenge that requires further investigation. In this letter, a specific aging test has been developed to monitor and characterize the electrical parameters of the SiC MOSFET. This allows estimations of the health state and predictions of the remaining lifetime prior to its failure. The gate leakage current seems to be a relevant runaway parameter just before failure. This leakage indicates deterioration of the gate structure. This hypothesis has been validated through analysis of scanning electron microscopy pictures, with a focused ion beam cut showing cracks within the polysilicon.

Feol low-k spacers

Abstract: Transistors and their methods of formation are described. Low dielectric constant material (e.g. a void) is placed between an elongated gate and a contact to increase the attainable switching speed of the gate of the device. An elongated structural slab of silicon nitride is temporarily positioned on both sides of the gate. Silicon oxide is formed over the silicon nitride slabs and the gate. Contacts are formed through the silicon oxide. The silicon oxide is selectively etched back to expose the silicon nitride slab. A portion or all the silicon nitride slab is removed and replaced with low-K dielectric or any dielectric with an air-gap to enable higher switching speed of the transistor. The highly-selective silicon nitride etch uses remotely excited fluorine and a very low electron temperature in the substrate processing region.

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Abstract: Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

Multi-channel gate-all-around FET

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

High-Voltage and Low-Leakage-Current Gate Recessed Normally-Off GaN MIS-HEMTs With Dual Gate Insulator Employing PEALD- ${\rm SiN}_{x}$ /RF-Sputtered- ${\rm HfO}_{2}$

Abstract: To fabricate gate recessed normally-off AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors, we have employed a novel SiNx/HfO2 dual gate insulator. A plasma enhanced atomic layer deposition (PEALD) technique was used for very thin high quality SiNx (5 nm) as an interfacial layer followed by RF-sputtered HfO2 as a high- k dielectric for the second gate insulator structure. The PEALD SiNx interfacial layer effectively suppresses the forward gate leakage current and the current collapse. We have achieved excellent characteristics such as large threshold voltage of 1.65 V, high breakdown voltage of 900 V, extremely small off-state drain leakage current less than 10-9 A/mm and high ON/OFF drain current ratio of ~ 109, low on-state resistance of 1.84 mΩ·cm2, and small subthreshold slope of 85 mV/decade.

High mobility field effect transistor based on BaSnO3 with Al2O3 gate oxide

Abstract: We fabricated an n-type accumulation-mode field effect transistor based on BaSnO3 transparent perovskite semiconductor, taking advantage of its high mobility and oxygen stability. We used the conventional metal-insulator-semiconductor structures: (In,Sn)2O3 as the source, drain, and gate electrodes, Al2O3 as the gate insulator, and La-doped BaSnO3 as the semiconducting channel. The Al2O3 gate oxide was deposited by atomic layer deposition technique. At room temperature, we achieved the field effect mobility value of 17.8 cm2/Vs and the Ion/Ioff ratio value higher than 105 for VDS = 1 V. These values are higher than those previously reported on other perovskite oxides, in spite of the large density of threading dislocations in the BaSnO3 on SrTiO3 substrates. However, a relatively large subthreshold swing value was found, which we attribute to the large density of charge traps in the Al2O3 as well as the threading dislocations.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

Abstract: In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

Abstract: In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current $(I_{{\scriptstyle {\rm ON}}})$ , a better ON-state to OFF-state current $(I_{{\scriptstyle {\rm ON}}}/I_{{\scriptstyle {\rm OFF}}})$ ratio, and a better subthreshold slope.

Integrated circuit having multiple threshold voltages

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Gate Capacitance-Dependent Field-Effect Mobility in Solution-Processed Oxide Semiconductor Thin-Film Transistors

Abstract: Solution-processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin-film transistors (TFTs). In order to produce high-performance and long-sustainable portable devices with the solution-processed OS TFTs, the low-operational voltage driving current is a key issue. Experimentally, increasing the gate-insulator capacitances by high-k dielectrics in the OS TFTs has significantly improved the field-effect mobility of the OS TFTs. But, methodical examinations of how the field-effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field-effect mobility on the gate capacitances in the solution-processed OS TFTs is presented, where the multiple-trapping-and-release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single-piece expression showing how the field-effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field-effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field-effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.

4H-SiC Trench MOSFET with Bottom Oxide Protection

Abstract: Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (Eox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (Cgd). The grounded BPW is found to be an effective means of both suppressing Eox and reducing switching loss.

Semiconductor structures with coplanar recessed gate layers and fabrication methods

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Integrated circuits with selective gate electrode recess

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET

Abstract: In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas.

Solution-processed amorphous hafnium-lanthanum oxide gate insulator for oxide thin-film transistors

Abstract: Solution-processed high-K dielectrics for oxide thin-film transistors (TFTs) have been widely studied with the objective of achieving high performance and low-cost TFTs for next-generation displays. In this study, we introduce an amorphous hafnium-lanthanum oxide (HfLaOx) gate insulator with high electrical permittivity which was fabricated by the simple spin-coating method. In particular, the solution-processed HfLaOx dielectric layer, which was achieved by a mixture of two Hf and La metal hydroxide precursors, showed amorphous properties, a low leakage current and a high dielectric constant. The solution-processed HfLaOx dielectric layers showed a breakdown voltage as high as 5 MV cm−1 in strength and a dielectric constant above 22. Based on their implementation as a gate insulator, the solution-processed ZnO/HfLaOx TFTs showed good and stable performances during operation at a low voltage. A mobility of μ = 1.6 cm2 V−1 s−1, an on/off current ratio of 106, and a threshold voltage of 0.0015 V were obtained under a 5 V gate bias. Our results show the possibility of the solution-processed amorphous HfLaOx dielectric layer as a gate insulator for oxide TFTs. We believe that this amorphous HfLaOx dielectric has good potential for next-generation high-performance TFT devices.

High-Speed Resonant Gate Driver With Controlled Peak Gate Voltage for Silicon Carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a silicon carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200-V silicon carbide MOSFET gate driver are presented, demonstrating the switching loss of 230 μJ at 800 V and 10 A. This represents a 20% reduction in switching losses in comparison to that of conventional gate drive methods.