Showing papers on "Gate oxide published in 2018"

Evolution of Total Ionizing Dose Effects in MOS Devices With Moore’s Law Scaling

Abstract: The general reduction in the thicknesses of critical dielectric layers driven by Moore’s law scaling has led to increasingly more manageable total-ionizing-dose (TID) response over the last ~50 years. Effects of oxide, interface, and border traps in MOS gate oxides on TID response are now mostly well known for SiO2 gate dielectrics, and the leakage currents due to isolation oxides can be conservatively bounded with existing test methods. Radiation hardened and/or radiation-tolerant technologies have been developed that can survive doses that exceed 1 Mrad(SiO2). Advances in computing technology enabled by Moore’s law scaling and concomitant enhancements in computational techniques have greatly facilitated the modeling and simulation of TID effects in microelectronic devices and ICs. However, the TID response of nanoscale MOS devices with advanced gate stacks and high- ${K}$ gate dielectrics, and/or alternative materials to Si, is often more complex than for MOS devices with SiO2 gate oxides. TID challenges remain for linear bipolar technologies that exhibit enhanced low-dose-rate sensitivity and for microelectronic devices that must function at doses above ~100 Mrad(SiO2), e.g., in high luminosity accelerator environments. TID effects have also recently been observed in wide bandgap semiconductor devices (e.g., GaN/AlGaN HEMTs) with no gate oxide.

Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer MoS2 field-effect transistors

Abstract: While two-dimensional (2D) van der Waals (vdW) layered materials are promising channel materials for wearable electronics and energy-efficient field-effect transistors (FETs), large hysteresis and large subthreshold swing induced by either dangling bonds at gate oxide dielectrics and/or trap molecules in bubbles at vdW interface are a serious drawback, hampering implementation of the 2D-material based FETs in real electronics. Here, we report a monolayer MoS2 FET with near-zero hysteresis reaching 0.15% of the sweeping range of the gate bias, a record-value observed so far in 2D FETs. This was realized by squeezing the MoS2 channel between top h-BN layer and bottom h-BN gate dielectrics and further removing the trap molecules in bubbles at the vdW interfaces via post-annealing. By segregating the bubbles out to the edge of the channel, we also obtain excellent switching characteristics with a minimum subthreshold swing of 63 mV/dec, an average subthreshold slope of 69 mV/dec for a current range of four orders of magnitude at room temperature, and a high on/off current ratio of 108 at a small operating voltage (<1 V). Such a near-zero hysteresis and a near-ideal subthreshold limit originate from the reduced trap density of ~5.2 × 109 cm−2 eV−1, a thousand times smaller than previously reported values.

Understanding BTI in SiC MOSFETs and Its Impact on Circuit Operation

Abstract: The threshold voltage hysteresis in SiC power MOSFETs is rarely studied. This paper investigates the captureand emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias. We present a measurement technique which enables time-resolved measurement of the real ${V} _{\text {th}}$ during application-relevant bipolar ac high temperature gate stress. In addition, we use capture and emission time maps to explain the temperature dependence of $\Delta {\text V}_{\text {th}}$ after stress and are able to simulate $\Delta {\text V}_{\text {th}}$ after positive ac stress considering the full stress-history. Furthermore, we will show that the threshold voltage hysteresis has no harmful impact on switching operation in real applications.

Influence of LDD Spacers and H + Transport on the Total-Ionizing-Dose Response of 65-nm MOSFETs Irradiated to Ultrahigh Doses

Abstract: The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. Ionization in the spacer oxide and overlying silicon nitride layers above the lightly doped drain extensions leads to charge buildup as well as the ionization and/or release of hydrogen. Charge trapped in the spacer oxide or at its interface modifies the parasitic series resistance, reducing the drive current. The released hydrogen transports as H+ with an activation energy of ~0.92 eV. If the direction of the electric field is suitable, the H+ can reach the gate oxide interface and depassivate Si-H bonds, leading to threshold voltage shifts. Newly created interface traps are most prominent near the source or drain. The resulting transistor responses and defect-energy distributions often vary strongly in space and energy as a result, as demonstrated through current–voltage, charge-pumping, and low-frequency noise measurements.

2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

Abstract: A continuous 2-D analytical drain current model of double-gate (DG) heterojunction tunnel field-effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures has been presented in this paper. The surface potential model has been developed by considering the effect of accumulation/inversion charges and depletion region at source/channel and drain/channel junctions. The electric field-dependent band-to-band tunneling generation rate has been derived from the surface potential model. The tangent line approximation method has been used to calculate the drain current of DG HJTFETs. The developed model is valid for all regions (subthreshold to strong accumulation/inversion region) of operation. The model has been developed for Si/Ge hetero and Si homojunction-based tunnel field-effect transistor devices. The model is also applicable for other structures such as III–V materials-based InAs/GaSb DG HJTFET and silicon-on-insulator-based HJTFET. The analytical model results are validated by 2-D ATLAS simulation data.

A Gate Driver of SiC MOSFET for Suppressing the Negative Voltage Spikes in a Bridge Circuit

Abstract: SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet , which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfet s under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated.

Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same

Abstract: Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOx layer over the second silicon oxy-nitride layer and ILs.

Reliability studies of SiC vertical power MOSFETs

Abstract: Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation, with high MOS gate oxide field in the on-state, and high drift and termination fields in the blocking state. Moreover, silicon carbide devices typically experience higher fields than comparable Si devices due to channel and drift property differences. SiC MOSFET threshold voltage stability and gate oxide lifetime under high gate oxide field are observed to follow the same functional form as Si devices. SiC MOSFETs demonstrate intrinsic oxide lifetime greater than 107 hrs in time-dependent dielectric breakdown (TDDB) testing. Accelerated high-temperature reverse-bias (HTRB) testing above the rated voltage reveals similarly long lifetime under high drift fields. The device failure rate due to terrestrial neutron single-event burnout (SEB) is shown to be comparable or superior to that of Si devices. Results demonstrate the reliability of SiC MOSFETs under high-field operation.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Abstract: Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound)

Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs

Abstract: Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.

Real-Time Junction Temperature Sensing for Silicon Carbide MOSFET With Different Gate Drive Topologies and Different Operating Conditions

Abstract: The switching transient properties from the switching power semiconductor gate side are sensitive to the device's junction temperature ( $T_{j}$ ) Real-time $T_{j}$ sensing methods based on gate drive switching transient properties have been investigated on silicon MOSFET and silicon IGBT, with a conventional push–pull-type gate drive, under fixed dc-bus voltage In this paper, this method is applied to silicon-carbide (SiC) MOSFET The $T_{j}$ sensing methods are evaluated with different types of gate drive topologies By implementing the SiC MOSFETs into an H-bridge inverter, the effect of dc-bus voltage for the $T_{j}$ sensing method is investigated Different “gate drive−semiconductor” dynamic models are built, including gate drive output power stage, gate drive parasitics, SiC MOSFET intrinsic parameters, and PCB parasitics Experimental results are compared with circuit LTSpice model simulation The device vertical temperature contours are evaluated Suitable circuitry for $T_{j}$ sensitivity extraction is provided

Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET

Abstract: In this paper, the temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET (HD GAA TFET) has been addressed, and the results are simultaneously compared with gate all around tunnel FET (GAA TFET). This is done by investigating the effect of interface trap charges such as donor (positive interface charges) and acceptor (negative interface charges) at various operating temperatures on the device analog parameters and RF figure of merits. It is observed that, at high gate bias, TFET exhibits weak temperature dependence owing to the weak dependence of band to band tunneling phenomenon on the temperature in comparison to the large temperature variation for lower gate bias due to the temperature dependence of Shockley-Read-Hall (SRH) phenomenon. Results reveal that extremely high off current at elevated temperatures degarades the device performance, making the device less reliable for high-temperature applications. Moreover, at elevated temperature, the decrease in threshold voltage and intrnsic delay, and increase in cut off frequency is found, thereby upgrading the device characteristics. All the simulations have been done on ATLAS device simulator.

SiC power MOSFET gate oxide breakdown reliability — Current status

Abstract: SiC power MOSFET is poised to take off commercially. Gate oxide breakdown reliability is an important obstacle standing is the way. Early prediction of poor intrinsic reliability comparing to silicon MOSFET, while theoretically sound, has now proven way too pessimistic. Experimental data from good quality SiC MOSCAP turns out to have better breakdown lifetime than its silicon counterpart, based on data available in the literature. This surprising result is the consequence of improper extraction of intrinsic lifetime in the presence of extrinsic failures. Even though intrinsic lifetime is no longer an issue, SiC MOSFET gate oxide breakdown reliability is not out of the wood yet. This is because, for thick oxide, it is the extrinsic failure that determine lifetime, not intrinsic failure. Unfortunately, up to now there is no properly done study of SiC gate oxide extrinsic breakdown study reported in the literature.

Miller plateau as an indicator of SiC MOSFET gate oxide degradation

Abstract: This paper presents a new indicator of SiC MOSFET gate oxide degradation based on Miller plateau. The physical mechanism of Miller plateau shift with gate oxide electric field is first analyzed. The relationship between Miller plateau and ambient temperature is then explored by theoretical analysis. The electro-thermal simulation is conducted in LTSpice to verify the Miller plateau shift with ambient temperature. Besides, 20 groups of High Electric Field (HEF) acceleration tests are conducted with V gs stress amplitude of 25 V, 30V, 35V, 40V and stress duration of 10, 40, 70, 85, 100 hours. 5 SCT2120AF SiC MOSEFTs from Rohm are stressed in each group. After ageing tests, the stressed devices are used to verify dynamic characteristic change in the designed double pulse test platform. After 100-hour HEF tests with 40V V gs stress, Miller plateau shift can reach up to 1.5V. Finally, comparison is made among Miller plateau, threshold voltage and gate resistor turn-on energy. Analysis shows that Miller plateau can be used as an indicator of SiC MOSFET gate oxide degradation with detectable amplitude shift as well as inherent gate driver integration and online monitoring characteristics.

Water assisted atomic layer deposition of yttrium oxide using tris(N,N′-diisopropyl-2-dimethylamido-guanidinato) yttrium(III): process development, film characterization and functional properties

Abstract: We report a new atomic layer deposition (ALD) process for yttrium oxide (Y2O3) thin films using tris(N,N′-diisopropyl-2-dimethylamido-guanidinato) yttrium(III) [Y(DPDMG)3] which possesses an optimal reactivity towards water that enabled the growth of high quality thin films Saturative behavior of the precursor and a constant growth rate of 11 A per cycle confirm the characteristic self-limiting ALD growth in a temperature range from 175 °C to 250 °C The polycrystalline films in the cubic phase are uniform and smooth with a root mean squared (RMS) roughness of 055 nm, while the O/Y ratio of 20 reveal oxygen rich layers with low carbon contaminations of around 2 at% Optical properties determined via UV/Vis measurements revealed the direct optical band gap of 556 eV The valuable intrinsic properties such as a high dielectric constant make Y2O3 a promising candidate in microelectronic applications Thus the electrical characteristics of the ALD grown layers embedded in a metal insulator semiconductor (MIS) capacitor structure were determined which resulted in a dielectric permittivity of 11, low leakage current density (≈10−7 A cm−2 at 2 MV cm−1) and high electrical breakdown fields (40–75 MV cm−1) These promising results demonstrate the potential of the new and simple Y2O3 ALD process for gate oxide applications

Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET

Abstract: In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages. The structure is based upon asymmetric gate oxide structure by combining silicon dioxide (SiO2) gate dielectric at source side and vacuum dielectric at drain side, which significantly reduces BTBT and OFF-state gate leakages, thereby making it suitable for low-power applications. It is examined that GIDL i.e., an OFF-state leakage phenomenon, is reduced in DM-HD GAA MOSFET by lowering the BTBT. This can be done by reducing OFF-state leakages due to: 1) increase in tunneling width and 2) increased barrier height from source to channel. The results show that the OFF-state leakage current in DM-HD GAA MOSFET reduces to an order of $10^{-\textsf {13}}$ over $10^{-\textsf {9}}$ A as in the case of conventional GAA MOSFET. The results so obtained are compared with those of cylindrical dual-metal GAA (DM-GAA) MOSFET and GAA MOSFET to analyze its performance. OFF-state leakages at higher temperatures have also been analyzed.

Modeling Short-Channel Effects in Asymmetric Junctionless MOSFETs With Underlap

Abstract: This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications.

Demonstration of a Curable Nanowire FinFET Using Punchthrough Current to Repair Hot-Carrier Damage

Abstract: Device degradation caused by gate oxide damage in a FinFET on silicon-on-insulator is recovered using punchthrough current via a silicon fin. As the high level of drain current flows under a punchthrough mode, localized Joule heat driven by drain current, enough to anneal the gate oxide, is induced in the channel. This selectively cured localized damage in the FinFET. The dependence of recovery on the gate length, substrate material underneath the channel, and the proper range of annealing voltage are investigated.

Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative Capacitance FET Using Capacitance Matching

Abstract: In this paper, approaches to obtain the sub- kT/q non-hysteretic operation mode in negative capacitance (NC) field-effect-transistors for a wide band of applied gate voltages, using capacitance matching, were systematically investigated using TCAD simulation. Unlike certain previous studies, in which the desired operation conditions were received for specific structures and materials, this study presents for the first time a general approach for matching arbitrary MOSFETs with various ferroelectric (FE) materials. This study shows that depending on the initial capacitance matching which represents the best possible subthreshold slope for the preliminary chosen base structure and FE material, any further optimization process can be different. Additionally, for the first time, FE materials were grouped with respect to the shape of their C–V curves in the NC region. This paper shows that with respect to the base structure, certain types of FEs are more preferable to obtain the sub- kT/q operation in a non-hysteretic manner for the wide band of applied voltages. In addition, the impacts of various parameters including the depletion capacitance, supply voltage, gate oxide capacitance, buried oxide capacitance on the capacitance matching were systematically investigated.

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis.

Abstract: Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimising the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled also taking into account the interface state density in a tunnelling relaxation model and it allowed us to locate traps within a tunnelling distance of up to 1.3 nm from the SiO2/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a non-abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiO x matrix. A mixed sp2/sp3 carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

Abstract: This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the $$\hbox {SiO}_{2}$$ dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by $$+$$ 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.

A Study on the Impact of Channel Mobility on Switching Performance of Vertical GaN MOSFETs

Abstract: This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$ ) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions.

In 0.53 Ga 0.47 As FinFET and GAA-FET With Remote-Plasma Treatment

Abstract: This letter presents a remote NH3/N2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current ( ${I}_{\textsf {DS}}$ ), transconductance ( ${G}_{m}$ ), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

Abstract: We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices.

Abstract: We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1−x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1−x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices.

Impact of the Gate Oxide Reliability of SiC MOSFETs on the Junction Temperature Estimation Using Temperature Sensitive Electrical Parameters

Abstract: Bias temperature instability (BTI) is more problematic in SiC power MOSFETs due to the occurrence of higher interface state traps and fixed oxide traps compared to traditional silicon MOS interfaces where there are no carbon atoms degrading the atomically smooth Si/SiO 2 interface. The use of temperature sensitive electrical parameters (TSEPs) for measuring the junction temperature and enabling health monitoring based on junction temperature identification is a promising technique for increasing the reliability of power devices, however in the light of increased BTI in SiC devices, this must be carefully assessed. This paper evaluates how BTI of SiC power MOSFETs under high temperature gate bias stresses affects the electrical parameters used as TSEPs and its impact on condition monitoring.

Total Ionizing Dose Response and Annealing Behavior of Bulk nFinFETs With ON-State Bias Irradiation

Abstract: The total ionizing dose response of bulk nFinFETs with multiple gate lengths and multiple fins is investigated for on-state bias condition. Experiments and Technology Computer Aided Design simulations were performed to analyze the effect of the trapped charges in the gate oxide and shallow trench isolation (STI) oxide on the threshold voltage and transconductance of the devices. The increases in the threshold voltage and transconductance are observed after X-ray irradiation. The positive shift of the threshold voltage is caused by the net negative charges trapped in the gate oxide. The simulation results show that the trapped holes in the STI oxide reduce the electric field and increase the electron mobility in channel near the fin bottom, which is the major contribution to the increased transconductance. An interesting phenomenon was also observed that the threshold voltage continues to increase during the annealing process, whereas the transconductance decreases. These results suggest that there may also be a small amount of trapped holes in gate oxide during irradiation, and those trapped holes are compensated by electrons transporting from the silicon during the anneal, leading to further positive shift of the threshold voltage. Moreover, the decrease in transconductance is mainly introduced by the neutralization of the trapped holes at STI/silicon interface.