Showing papers on "Gate oxide published in 2019"

Current Aperture Vertical $\beta$ -Ga 2 O 3 MOSFETs Fabricated by N- and Si-Ion Implantation Doping

Abstract: Depletion-mode vertical Ga2O3 metal-oxide-semiconductor field-effect transistors featuring a current aperture were developed on a halide vapor phase epitaxial drift layer grown on a bulk $\beta $ -Ga2O3 (001) substrate. Three ion implantation steps were employed to fabricate the ${n}^{++}$ source regions, lateral ${n}$ channel, and ${p}$ current blocking layers, where Si and N were selected as the donor and deep acceptor dopant species, respectively. The transistors delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 $\text{m}\Omega \cdot \text {cm}^{2}$ , and an output current on/off ratio of over 108. High-voltage performance of the present devices was hampered by a large gate oxide field in the off-state causing high gate leakage, a limitation that can be readily overcome through optimized doping schemes and an improved gate dielectric. The demonstration of a planar-gate vertical Ga2O3 transistor based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics.

Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO 2 Oxide

Abstract: We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current ( ${I}_{ \mathrm{OFF}}$ ) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$ . Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes.

Degradation Assessment and Precursor Identification for SiC MOSFETs Under High Temp Cycling

Abstract: Silicon carbide (SiC) power mosfet s are promising alternatives to Si devices in high-voltage, high-frequency, and high-temperature applications. The rapid and widespread deployment of SiC devices raises long-term reliability concerns, particularly for mission and safety critical systems due to limited field data and potential uncertainties. Therefore, it is essential to investigate progressive degradations and parameter shifts in SiC devices to develop system integrated degradation monitoring tools for self-monitoring converters, which can recognize failure precursors at the earliest stage and prevent catastrophic failures. This paper presents a comprehensive long-term reliability analysis of commercially available SiC mosfet s under high temperature operation and high temperature swing, degradation related key precursors, and possible causes behind them. For this purpose, discrete SiC devices are power cycled and all datasheet parameters are recorded at certain intervals with the aid of the curve tracer. Variation of electrical parameters throughout the tests is presented in order to assess their correlation with the aging/degradation state of the switch. Among them, gate oxide charge trapping related threshold voltage drift and corresponding on state resistance variation has been observed for all samples. For some samples, bond wire heel cracking is found to be the root cause of sudden on state resistance and body diode voltage increases. The discussions regarding aging precursors are supported by failure analysis obtained through the decapsulation of failed devices. Finally, the findings are evaluated in order to define the suitability of electrical parameters as an aging precursor parameter under the light of practical implementation related issues.

Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering

Abstract: This paper is about the compared performance investigation of various structures of Hetero-Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate Oxide (DHGO), Triple Hetero Gate Oxide (THGO) and Quadruple Hetero Gate Oxide (QHGO) to produce lower leakage current, higher Ion/Ioff ratio, higher gm/gd and also lower Drain Induced Barrier Lowering (DIBL) than those of a conventional triple-gate FinFET. Among all of them, the best results are explored for the DHGO FinFET structure. In DHGO FinFET structure, a high-κ dielectric (κ = 22) is used on the top oxide to increase the gate control and a low-k dielectric (κ = 3.9) is used over silicon body owing to the compatibility of lattice constant of SiO2 and silicon. Mode-space drift-diffusion (DD_MS) model coupled with Schrodinger equation has been utilized in order to analyze the proposed and conventional structures in three dimensional (3D) simulation domain. Interestingly, by decreasing the thickness of the oxide layer and increasing the permittivity coefficient, the leakage current decreases, thus increasing the Ion/Ioff ratio. The DHGO FinFET structure is found to exhibit higher Ion/Ioff, lower DIBL and higher gm/gd ratio, thus proving performance superiority over the other conventional junctionless FinFET and also MOSFETs.

Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power MOSFET s Under Repetitive Avalanche Shocks

Abstract: In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage ( Cg – Vg ) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO2 interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance ( C gd) under low drain-source voltage ( V ds) bias condition. It further takes responsibilities for the increments in input capacitance ( Ciss ), output capacitance ( Coss ), and reverse transfer capacitance ( Crss ). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn- off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn- on and turn- off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.

Design and Analysis of a Heterojunction Vertical t-Shaped Tunnel Field Effect Transistor

Abstract: In this paper, a heterojunction vertical t-shaped tunnel field effect transistor (V-tTFET) is proposed, and the scaling issue associated with it is investigated using Sentaurus Technology computer-aided design simulation. This device is basically a gated P-I-N diode. It is made up of silicon material with dual gate control over the channel based on a band-to-band tunneling mechanism. Furthermore, a silicon-germanium (SiGe) layer is introduced to the channel which results in an aggressive improvement in the input characteristics of the device. The testified results of the device with respect to threshold voltage (VT), subthreshold slope and the current ratio (Ion/Ioff) emerges efficiently with the values of 0.253 V, 31.05 mV/decade and 1012 for a 60-nm channel length with a 10-nm SiGe layer. A lower bandgap material in the source region and higher bandgap material in the drain region also improves the input characteristics of the device. It is also demonstrated that scaling the gate oxide thickness (tox) enhances the device characteristics. Moreover, ON-state current increases exponentially by taking the high value of the dielectric constant (k) for the oxide material. Furthermore, the (p++) source doping concentration of the V-tTFET lies between 1018 to 1020 cm−3 which makes the tunneling easier at the source-channel junction to achieve high Ion/Ioff. The vertical tunnel FET has a distribution of the source channel drain in the vertical direction, which enhances the scalability of the simulated device.

Analytical Modeling of a Triple Material Double Gate TFET with Hetero-Dielectric Gate Stack

Abstract: In this paper, we propose and develop an analytical model of a Triple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-dielectric gate oxide stack comprising of SiO2 and HfO2. The two-dimensional Poisson’s equation has been solved using parabolic-approximation method to model the channel potential and electric field. Analytical model of drain current is developed by integrating the band-to-band tunneling generation rate over the channel thickness (tsi) and shortest tunneling path ($L_{\min }$). A Transconductance model is also developed using this drain current model. The proposed TM-DG TFET also provides better result with reference to input-output characteristics, subthreshold swing, ION/IOFF current ratio and ambipolar effect compared to the dual material double gate (DM-DG) TFET. The analytical model has been validated with the numerical data obtained from commercial TCAD software.

Gate Damages Induced in SiC Power MOSFETs During Heavy-Ion Irradiation—Part II

Abstract: This article presents the results of a 2-D finite element simulation study of the gate damages induced by heavy-ion irradiation in SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The time evolution of the electric field in the gate oxide is studied. Two effects are investigated: the first is associated with the charge deposition in the SiC portion of the MOSFET, with the time evolution studied using the 2-D finite element simulator; the second one results from holes generated during the ion transit, trapped in the gate oxide after the fast electrons have been quickly swept away by the electric field. Two different techniques have been combined for estimating the hole concentration in the gate oxide: the well-known recombination rate was modified to consider the trapped charge yield, as was recently done to better interpret single event gate rupture (SEGR) failure of silicon power MOSFETs. Under ion irradiation test conditions at which the gate damage experimentally starts to be observed, we demonstrate that, because of the ion impact, regardless of the ion linear energy transfer (LET), the peak value of the electric field in the gate oxide becomes practically equal to the oxide breakdown field (~12–15 MV/cm). Moreover, we show that simulations can be used to predict the test conditions at which gate damage starts to appear as a function of LET and the range of heavy ions used in the irradiation experiments.

Current Transport Mechanism for Heavy-Ion Degraded SiC MOSFETs

Abstract: High sensitivity of silicon-carbide (SiC) power MOSFETs has been observed under heavy-ion irradiation, leading to permanent increase of drain and gate leakage currents. The electrical postirradiation analysis confirmed the degradation of the gate oxide and the blocking capability of the devices. At low drain bias, the leakage path is formed between drain and gate, while at higher bias the heavy-ion-induced leakage path is mostly from drain to source. An electrical model is proposed to explain the current transport mechanism for heavy-ion degraded SiC power MOSFETs.

Improvement in electrical characteristics of Silicon on Insulator (SOI) transistor using Graphene material

Abstract: This paper presents the electrical characteristics of a short channel Silicon on Insulator (SOI) transistor with a graphene layer. The graphene sheet is used at the bottom of the channel close to the source side and a proportionally heavily p-type retrograde doping implanted in nearly middle of the channel. To increase the gate electrostatic control over the channel we incorporated a high-K material i.e. HfO2 as the gate oxide insulator. Due to Graphene growth and Retrograde Doping in the Channel, we called this structure “GRDC-SOI” transistor. Because graphene sheet has low band gap and high mobility, we used it to increase the on-state current. Engineered p-type retrograde doping utilized for both decreasing off-state current and increasing on-state current. These dopants cause impurity scattering in the depth of the channel and deflect electron movements and decrease off-current. On the other hand, these dopants which are located almost in the middle of the channel can play the role of base in an NPN Bipolar Junction Transistor (BJT), and turn it on and exceed the on-state current. An immense comparison among our proposed device and a device similar to GRDC-SOI but without Graphene sheet (RDC-SOI) and a conventional structure shows that our proposed device has superior electrical characteristics in terms of ION/IOFF ratio, transconductance, subthreshold slope, leakage current, breakdown voltage and short channel effects like hot carriers injection and DIBL. Our analyses demonstrate that GRDC-SOI transistor can open a window for utilizing Graphene material in digital circuits and system on chip applications.

A System Engineering Approach Using FMEA and Bayesian Network for Risk Analysis—A Case Study

Abstract: This paper uses a system engineering approach based on the Failure Mode and Effect Analysis (FMEA) methodology to do risk analysis of the power conditioner of a Proton Exchange Membrane Fuel Cell (PEMFC). Critical components with high risk, common cause failures and effects are identified for the power conditioner system as one of the crucial parts of the PEMFCs used for backup power applications in the telecommunication industry. The results of this paper indicate that the highest risk corresponds to three failure modes including high leakage current due to the substrate interface of the metal oxide semiconductor field effect transistor (MOSFET), current and electrolytic evaporation of capacitor, and thereby short circuit, loss of gate control, and increased leakage current due to gate oxide of the MOSFET. The MOSFETs, capacitors, chokes, and transformers are critical components of the power stage, which should be carefully considered in the development of the design production and implementation stage. Finally, Bayesian networks (BNs) are used to identify the most critical failure causes in the MOSFET and capacitor as they are classified from the FMEA as key items based on their Risk Priority Numbers (RPNs). As a result of BNs analyses, high temperature and overvoltage are distinguished as the most crucial failure causes. Consequently, it is recommended for designers to pay more attention to the design of MOSFETs’ failure due to high leakage current owing to substrate interface, which is caused by high temperature. The results are emphasizing design improvement in the material in order to be more resistant from high temperature.

Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

Abstract: This paper examines a Junctionless quadruple gate (JLQG) MOSFET for analog and linearity distortion performance by numerically calculating transconductance and its higher order derivatives (gm1, gm2and gm3), VIP2, VIP3, IIP3 and IMD3. Influence of various physical device parameters: channel length, height (or width), gate oxide thickness, and channel doping concentration on the linearity distortion parameters are analyzed. From the numerical calculations it has been shown that the desirable characteristics for analog application at a given technology node are obtained for higher values of tSi, tox, and Nd. The present analysis also reveals the guidelines for the design of JLQG MOSFETs with least linearity distortion.

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing.

Abstract: In this paper, electrostatically configurable 2D tungsten diselenide (WSe2 ) electronic devices are demonstrated. Utilizing a novel triple-gate design, a WSe2 device is able to operate as a tunneling field-effect transistor (TFET), a metal-oxide-semiconductor field-effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band-to-band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self-consistent full-band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub-60 mV dec-1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low-power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.

Physical Origin of the Gate Current Surge During Short-Circuit Operation of SiC MOSFET

Abstract: During the short circuit of a vertical 4H-SiC power MOSFET, a high gate current starts to flow through the gate dielectric. We demonstrate that the Schottky emission is the main physical mechanisms.

Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

Abstract: In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET to enhance the device reliability Dual Metal Dielectric Engineered Gate All Around (DMDEGAA) MOSFET has been compared with both cylindrical Dual Metal Gate All Around (DMGAA) MOSFET and cylindrical Gate All Around (GAA) MOSFET DMDEGAA MOSFET has larger tunneling distance than other two devices which further reduces Band To Band Tunneling (BTBT) It reduces GIDL current over other devices directing immunity from the leakages along with higher Ion/Ioff ratio showing larger applicability for digital applications DMDEGAA MOSFET shows Subthreshold Slope (SS) close to 60 mV/decade and has higher transconductance (gm), higher Transconductance Generation Factor (TGF), higher early voltage (VEA), lower channel resistance (Rch), higher Current Gain (CG) and higher Maximum Transducer Power Gain (MTPG) for improved analog performance DMDEGAA MOSFET also poses higher Cut Off Frequency (fT), higher Frequency Transconductance Product (FTP) and lower Total Gate Capacitance (Cgg) showing its efficacy for high speed and high frequency applications

Investigation of 1200 V SiC MOSFETs' Surge Reliability.

Abstract: In this work, the surge reliability of 1200 V SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) from various manufactures has been investigated in the reverse conduction mode. The surge current tests have been carried out in the channel conduction and non-conduction modes. The experimental results show that the maximum surge currents that the devices can withstand are similar for both cases. It is found that short circuits occurred between the gate and the source in the failed devices. The characteristics of the body diode have also changed after the tests. By measuring the device characteristics after each surge current is applied, it can be concluded that the damages to the gate oxide layer and the body diode occurred only when the maximum surge current is applied. By decapping the failed devices and observing the cross section of the damaged cell, it is found that high temperature caused by excessive current flow through the devices during the surge tests is the main reason for the device failure. Finally, the TCAD simulation of the devices has been carried out to bring insight into the operation of the devices during the surge events.

Heterojunction Diode Shielded SiC Split-Gate Trench MOSFET With Optimized Reverse Recovery Characteristic and Low Switching Loss

Abstract: A split-gate SiC trench MOSFET with a hetero-junction diode (HJD) is proposed and numerically analyzed in this paper. The proposed structure features the HJD to effectively suppress the turn-on of the parasitic body diode and reduce the depletion region in the JFET area. A P+ shielding layer surrounding the HJD and the gate oxide layer is used to alleviate the concentration of the electric field under the gate trench and improve the switching performance. As a result, not only the breakdown voltage is increased by 20.8% at the same level of the on-state resistance but also the miller charge and the switching loss of the proposed structure are reduced by 52% and 39.1%, respectively when compared with those of the conventional SiC trench MOSFET.

Capture and emission mechanisms of defect states at interface between nitride semiconductor and gate oxides in GaN-based metal-oxide-semiconductor power transistors

Abstract: A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs.

Impact of ferroelectric on the electrical characteristics of silicon–germanium based heterojunction Schottky barrier FET

Abstract: This work investigates the impact of ferroelectric gate oxide on high-k gate dielectric with low band gap Silicon Germanium ferroelectric Schottky barrier FET (SiGe Fe-SBFET), has been qualitatively simulated. The present research focuses on major improvement over the conventional device in terms of drain current and reduced subthreshold swing and analog performances. The proposed device has been analyzed in terms of numerous device electrostatic parameters such as electric field and energy band diagram using a ferroelectric material. A novel approach of SiGe-Fe-SBFET provides an effective technique helps to increase the performance in terms of on-current and off-state current of the device. The SiGe-Fe-SBFET also provides high Ion/Ioff ratio of 4.188 × 1012 and low Subthreshold swing of 67 mV/dec in comparison with germanium (Ge) and silicon (Si) material based ferroelectric SBFET. Apart from this, the increasing of tunneling width for the drive of carriers in the drain-channel junction, which results in a reduction of ambipolar conduction in off-state with gate drain underlap. Further, the analog performances of proposed and conventional device are evaluated such as transconductance, intrinsic gate delay, output conductance and cut-frequency which is dependent of parasitic gate capacitances are also investigated through a 2D Silvaco Atlas simulator.

Impact of nonuniform gate oxide shape on TFET performance: A reliability issue

Abstract: Gate dielectric scaling is a vital key to improve the steep switching characteristics of TFETs. However, scaling down the oxide thickness causes high gate leakage current that cannot be neglected. The impact of the leakage current on the device operation can cause a serious reliability problem. In this paper, we have investigated the effect of nonuniform gate oxide thickness on the current as well as the high-frequency performance of TFETs. The focus of this paper is to demonstrate how to reduce effects of gate leakage current by using a taper shape gate oxide. The IV and CV characteristics are investigated regarding different nonuniform gate oxide graded shapes. Further, the ON and OFF currents and SS, as figures of merit for low standby power application, have been analyzed. Apart from this, the RF figure of merit in terms of unit-gain cutoff frequency (fT) is investigated.

High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators

Abstract: Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at low temperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long-term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Abstract: In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.

Modeling and Analysis of Electro-Thermal Impact of Crosstalk Induced Gate Oxide Reliability in Pristine and Intercalation Doped MLGNR Interconnects

Abstract: This work presents the electro-thermal analysis of crosstalk effects in pristine (undoped) and intercalation doped multilayer graphene nanoribbon interconnects (MLGNRs). A temperature dependent distributed $T-$ network model of MLGNR interconnects has been developed for analyzing the crosstalk induced effects. Further, a temperature-aware gate oxide reliability model has been proposed to compute the crosstalk induced overshoot/undershoot impact on ultra-thin gate oxide for CMOS devices in terms of failure-in-time (FIT) for side-contact (SC) pristine as well as top-contact (TC) Arsenic pentafluoride ( $AsF_{5}$ ), Ferric chloride ( $FeCl_{3}$ ) and Lithium ( $Li$ ) intercalation doped and undoped MLGNR interconnects. Subsequently, comparisons with $Cu$ -based interconnects are made over a range of chip operating temperature from 233K to 450K.

Retrograde p-Well for 10-kV Class SiC IGBTs

Abstract: In this paper, we propose the use of a retrograde doping profile for the p-well for ultrahigh voltage (>uexcl;10 kV) SiC IGBTs. We show that the retrograde p-well effectively addresses the punchthrough issue, whereas offering a robust control over the gate threshold voltage. Both the punchthrough elimination and the gate threshold voltage control are crucial to high-voltage vertical IGBT architectures and are determined by the limits on the doping concentration and the depth that a conventional p-well implant can have. Without any punchthrough, a 10-kV SiC IGBT consisting of retrograde p-well yields gate threshold voltages in the range of 6–7 V with a gate oxide thickness of 100 nm. Gate oxide thickness is typically restricted to 50–60 nm in SiC IGBTs if a conventional p-well with $1 \times 10^{17}$ cm−3 is utilized. We further show that the optimized retrograde p-well offers the most optimum switching performance. We propose that such an effective retrograde p-well, which requires low-energy shallow implants and thus key to minimize processing challenges and device development cost, is highly promising for the ultrahigh-voltage (>10 kV) SiC IGBT technology.

Device Noise Reduction for Silicon Nanowire Field-Effect-Transistor Based Sensors by Using a Schottky Junction Gate.

Abstract: The sensitivity of metal oxide semiconductor field-effect transistor (MOSFET) based nanoscale sensors is ultimately limited by noise induced by carrier trapping/detrapping processes at the gate oxide/semiconductor interfaces. We have designed a Schottky junction gated silicon nanowire field-effect transistor (SiNW-SJGFET) sensor, where the Schottky junction replaces the noisy oxide/semiconductor interface. Our sensor exhibits significantly reduced device noise, 2.1 × 10–9 V2 μm2/Hz at 1 Hz, compared to reference devices with the oxide/semiconductor interface operated at both inversion and depletion modes. Further improvement can be anticipated by wrapping the nanowire by such a Schottky junction, thereby eliminating all oxide/semiconductor interfaces. Hence, a combination of the low-noise SiNW-SJGFET device with a sensing surface of the Nernstian response limit holds promises for future high signal-to-noise ratio sensor applications.

Investigation of nBTI degradation on GaN-on-Si E-mode MOSc-HEMT

Abstract: In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.

Engineering High- k/SiGe Interface with ALD Oxide for Selective GeO x Reduction.

Abstract: Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x-rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al2O3 in contrast to HfO2 on SiGe; however, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al2O3/SiGe is investigated using atomic layer deposited (ALD) Al2O3 insertion into or on top of ALD HfO2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al2O3/SiGe and HfO2/SiGe interfaces with the insertion of Al2O3 into or on top of the HfO2 oxide. The data is consistent with the Al2O3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.

The Potential of SiC Cascode JFETs in Electric Vehicle Traction Inverters

Abstract: The benefits of implementing silicon carbide (SiC) devices in electric vehicle (EV) powertrains have been widely reported in various studies. New generations of SiC devices including planar MOSFETs, trench MOSFETs, and more recently, cascode JFETs have been released by various manufacturers. SiC cascode devices comprise low-voltage silicon MOSFETs for gate driving and high-voltage depletion mode SiC JFETs for voltage blocking. These devices are particularly interesting, because they avoid the known reliability issues of SiC gate oxide traps resulting in threshold voltage drifts. In this article, an EV powertrain is simulated using experimental measurements of conduction and switching energies of various SiC devices including 650-V trench, 900-V planar, and 650-V cascode JFETs. Unlike in previous articles where losses are calculated using models based on datasheet parameters, here static and dynamic measurements on power devices at different currents and temperatures are used to calculate losses over simulated driving cycles. Field-stop IGBTs are also evaluated. The 3-phase, 2-level inverter model is electrothermal by accounting for the measured temperature dependence of the losses and uses accurate thermal networks derived from datasheets. The converter efficiency and the thermal performance are compared for each device technology. The results show that SiC cascode JFETs have great potential in EV powertrain applications.

Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications

Abstract: An improved subthreshold analytical model of Germanium source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET Ge(SRC)-DH-DD-TM-SG-TFET is proposed. The dielectric gate oxide structure is comprised of Silicon-dioxide and Hafnium oxide. The high-K dielectric materials overcomes the Short Channel Effects caused by ultrathin silicon devices. The subthreshold analysis is carried out by solving a 2-D Poisson’s equation using the parabolic approximation method. The electrical characteristics of Ge(SRC)-DH-DD-TM-SG-Tunnel FET are analyzed using a 3-D Sentaurus TCAD device simulator and compared with the silicon based single halo and triple material surrounding gate TFET structures. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio of 106. Moreover, the influence of germanium/silicon in dual dielectric materials has reduced the tunneling barrier width and the ON current (10−4 A/μm) of the proposed device and improved at the level of CMOS transistors.