Showing papers on "Gate oxide published in 2022"

Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

Abstract: With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Online Gate-Oxide Degradation Monitoring of Planar SiC MOSFETs Based on Gate Charge Time

Abstract: Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method.

Design and investigation of dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal pocket TFET device as a label-free biosensor

Abstract: In this article, a dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal source pocket tunnel field-effect transistor (DM-TMGOS-ZHP-TFET) structure has been investigated for the application of label free-biosensor. This work explores the advantage of gate work function engineering along with the gate-oxide-stack approach for the ZHP-TFET for the first time. An asymmetric nano-cavity is created adjacent to the source-channel junction to immobilize the target biomolecules conjugation to the proposed device. The sensitivity of the device is thoroughly investigated in terms of average subthreshold swing (SS), threshold voltage (V th) and the switching ratio (I on/I off) of the proposed device with the variation of the dielectric constant value inside the nano-gap under the gate electrode. The device characteristics are investigated with different combinations of metal work functions to match the desired feature and sensitivity of the device. In addition, the sensitivity analysis of the proposed device is analyzed in the presence of both positive and negative charged biomolecules in the cavity region to study the charge effect on label-free detection of the device. A comparative study is conducted between a single metal gate (SMG) ZHP-DM-TFET biosensor with the DM-TMGOS-ZHP-TFET biosensor explores the advantage of gate-work function engineering with a gate-oxide-stack approach. Interestingly the DM-TMGOS-ZHP-TFET biosensor shows superior results with a high current ratio sensitivity of 103 which is ten times more than the SMG-ZHP-DM-TFET biosensor and this device also exhibits low subthreshold characteristics.

Gate Stress Polarity Dependence of AC Bias Temperature Instability in Silicon Carbide MOSFETs

Abstract: As the silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistor (MOSFET) develops, increasing efforts are placed on ac bias temperature instability (AC BTI). It was reported that AC BTI becomes significant when and only when the gate stress is bipolar. A detailed study is made in this article to reveal the underpinning mechanism. A physical model is proposed to explain on how and why the gate stress bipolar affects the threshold drift. It is found that the gate stress polarity has to be carefully defined. As the model shows, it is the bipolar electric field, rather than the gate voltage itself, that speeds up the threshold voltage drift. It is hoped that this study provides a stepping stone toward the eventual understanding and management of AC BTI.

Leakage Optimization of the Buried Oxide Substrate of Nanosheet Field-Effect Transistors

Abstract: In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet field-effect transistors (NSFETs) by locally inserting an oxide material only under the gate region. NSFETs with punchthrough stoppers (PTSs) doping of the substrate region have been widely adopted to reduce substrate leakage; however, band-to-band tunneling (BTBT) under negative bias remains a serious problem in such devices. By only inserting the oxide material under the gate region, the electric field from the gate to the drain–substrate junction is dispersed. Furthermore, since there is no oxide material under the source and drain (S/D) region, there is no stress reduction along the channel direction coming from the silicon-on-insulator (SOI) structure. We performed technology computer-aided design (TCAD) simulations, and the results show that the proposed structure effectively reduces both the tunneling current in the NSFET with PTS structure and the OFF-current in the NSFET without PTS structure, compared with those of conventional NSFETs.

Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress

Abstract: In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and on-state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of on-state resistance caused by thermal fatigue is observed.

Sensitivity Enhancement of Dual Gate FET Based Biosensor Using Modulated Dielectric for Covid Detection

Abstract: This paper presents a dual gate dielectric modulated FET (DGDMFET) biosensor with enhanced sensitivity for covid detection. In earlier literature, the biosensors are operated using the surface interaction with the virus biomolecules that are reflected through a channel or gate. The downside of these types of sensors has limited sensitivity. In this paper, we have considered that the change in the dielectric constant due to virus proteins results in a significant shift in the threshold voltage of FET. Enhancement of sensitivity is done by using the novel dual metal gate arrangement with different work functions (higher at the source end and lower at the drain end) and the chromic oxide (Cr2O3) layer, which is carved out vertically to form nanogap. At the same time, interface charge density is maintained nearly equal to 1.0 × 1011 cm−2 at the Si-SiO2 layer. To demonstrate the proposed biosensor, electrical parameters (electron concentration, surface potential, energy band distribution, and electric field) and the absolute percentage sensitivity of threshold voltage, subthreshold slope, ON current, and transconductance are evaluated and compared with related literature. The ATLAS device simulator is used for the simulation of the proposed device.

First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip

Abstract: In this work, we reported the integration of 10-V CMOS logic circuit, 20-V gate driver, and 600-V VDMOSFET on a 4H-SiC single chip for full SiC smart power ICs. This integration process features PMOSFET isolation (P-iso) from the high voltage substrate, local oxidation of SiC isolation between devices, dual gate oxide thickness, and P ⁺ poly-Si gate. It is demonstrated that the blocking capability of the P-iso structure can exceed 700 V and the switch of the VDMOSFET can be controlled by a 10-V signal through a 10-V to 20-V level shifter and a 20-V gate driver.

Status of Aluminum Oxide Gate Dielectric Technology for Insulated-Gate GaN-Based Devices

Abstract: Insulated-gate GaN-based transistors can fulfill the emerging demands for the future generation of highly efficient electronics for high-frequency, high-power and high-temperature applications. However, in contrast to Si-based devices, the introduction of an insulator on (Al)GaN is complicated by the absence of a high-quality native oxide for GaN. Trap states located at the insulator/(Al)GaN interface and within the dielectric can strongly affect the device performance. In particular, although AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) provide superior properties in terms of gate leakage currents compared to Schottky-gate HEMTs, the presence of an additional dielectric can induce threshold voltage instabilities. Similarly, the presence of trap states can be detrimental for the operational stability and reliability of other architectures of GaN devices employing a dielectric layer, such as hybrid MIS-FETs, trench MIS-FETs and vertical FinFETs. In this regard, the minimization of trap states is of critical importance to the advent of different insulated-gate GaN-based devices. Among the various dielectrics, aluminum oxide (Al2O3) is very attractive as a gate dielectric due to its large bandgap and band offsets to (Al)GaN, relatively high dielectric constant, high breakdown electric field as well as thermal and chemical stability against (Al)GaN. Additionally, although significant amounts of trap states are still present in the bulk Al2O3 and at the Al2O3/(Al)GaN interface, the current technological progress in the atomic layer deposition (ALD) process has already enabled the deposition of promising high-quality, uniform and conformal Al2O3 films to gate structures in GaN transistors. In this context, this paper first reviews the current status of gate dielectric technology using Al2O3 for GaN-based devices, focusing on the recent progress in engineering high-quality ALD-Al2O3/(Al)GaN interfaces and on the performance of Al2O3-gated GaN-based MIS-HEMTs for power switching applications. Afterwards, novel emerging concepts using the Al2O3-based gate dielectric technology are introduced. Finally, the recent status of nitride-based materials emerging as other gate dielectrics is briefly reviewed.

Stacked Single Gate SOI 4H‐SiC Junctionless FET with a Buried P‐type 4H‐SiC layer

Abstract: This study describes a single-gate silicon on insulator junctionless metal–oxide–semiconductor field-effect transistor (SJL-MOSFET) with inserted buried 4H-SiC p-type layer (B-SJL-MOSFET). The embedded p-type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off-state mode. The p-type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high-k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p-type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on-state current (Ion) and improves the SS. Improvement of off-current is due to higher barriers between source-channel side and reduces the parasitic BJT in the off-mode.

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Abstract: This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

Nonvolatile memory characteristics associated with oxygen ion exchange in thin-film transistors with indium-zinc oxide channel and HfO2-x gate oxide

Abstract: Non-charge-storage-based nonvolatile memory characteristics associated with oxygen ion exchange are demonstrated in a thin-film transistor (TFT) composed of an indium-zinc oxide (IZO) channel and an oxygen-deficient HfO2–x gate oxide. A nonvolatile increase in drain current and a reduced threshold voltage are obtained upon application of positive gate voltage, with the opposite characteristics upon application of negative voltage. The device shows nonvolatile retention properties and suitable endurance properties after repeated operations. Modulation of channel conductance occurs as a results of oxygen ion exchange between the HfO2–x gate oxide and the IZO channel, which consequently alters the oxygen vacancy concentration in the IZO channel; these vacancies act as n-type dopants. For comparison, a device with a thin SiO2 layer inserted between the HfO2–x gate oxide and the IZO channel to prevent oxygen ion exchange shows only the increased threshold voltage upon application of a positive gate voltage as a result of electron charging. These results verify the conductance modulation mechanism associated with oxygen ion exchange at the interface of the HfO2–x gate oxide and the IZO channel. In addition, the nonvolatile memory characteristics of the device are indicative of its potential for non-charge-storage-based nonvolatile memory application.

Study on a novel vertical enhancement-mode Ga₂O₃ MOSFET with FINFET structure

Abstract: Abstract A novel enhanced mode (E-mode) Ga 2 O 3 metal–oxide–semiconductor field-effect transistor (MOSFET) with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated. It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics. The metal material of the gate, the oxide material, the oxide thickness, and the epitaxial layer concentration strongly affect the threshold voltage and the output currents. Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant. When the output current density of the device increases, the source concentration, the thickness of the epitaxial layer, and the total width of the device need to be expanded. The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage. It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga 2 O 3 MOSFET requires the epitaxial layer concentration, the channel height of the device, the thickness of the source region, and the oxide thickness of the device should be less than 5 × 10 16 cm −3 , less than 1.5 μm, between 0.1 μm − − 0.3 μm and less than 0.08 μm, respectively.

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Abstract: This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

Improvement in Instability of Transparent ALD ZnO TFTs Under Negative Bias Illumination Stress With SiO/AlO Bilayer Dielectric<sub /> <sub /> <sub />

Abstract: The theory of oxygen vacancy related deep energy defects and valence band offset (VBO) between gate insulator and channel codetermining the threshold voltage shift (ΔVTH) of ZnO thin film transistor under negative gate bias and illumination stress (NBIS) is proposed and investigated systematically. Two kinds of ZnO thin film transistors are fabricated by atomic layer deposition with different gate oxide structures, a control sample with Al2O3 gate oxide and an improved sample with SiO2/Al2O3 gate oxide structures. Among two kinds of devices, the device with SiO2/Al2O3 gate oxide achieves a smaller ΔVTH under the NBIS with SiO2 thin film acting as a holes-blocking layer, despite the existence of more defects than control device. The improvement in stability is attributed to large VBO up to 3.08 eV. Moreover, the device with SiO2/Al2O3 gate oxide is evaluated on a 500-nit LCD back light to simulate the practical working environment in displays, which exhibits good stability of ΔVTH = -0.3 V for 3600 seconds.

The Influence of 10 MeV Proton Irradiation on Silicon Carbide Power Metal-Oxide-Semiconductor Field-Effect Transistor

Abstract: The effects of 10 MeV proton irradiation on the threshold voltage and gate oxide reliability of SiC MOSFET are investigated. The negative shift of the threshold voltage was observed after irradiation, and the magnitude of the shift is exclusively related to the fluence and not the drain voltage. Moreover, proton irradiation leads up to the degeneration of oxide reliability. Experiment and simulation results indicate that the shift of the threshold voltage is caused by the total ionizing dose effect. Due to the superior blocking capabilities of the SiC MOSFET, the electric field of gate oxide is almost unaffected by the voltage applied to the drain, so the drift of threshold voltage is only related to particle fluence. The single event effect is responsible for the degradation of gate oxide reliability. The single event effect induces a transient high electric field in the gate oxide, which generates defects and affects the reliability of the gate oxide.

Cold Carrier Injection Mechanism for Gate Oxide Integrity of High Voltage NDMOS

Abstract: This article studies a reliability mechanism for field-plate-assisted reduced surface field (RESURF) effect 225-V NDMOS devices based on anode hole oxide injection for carriers that are in thermal equilibrium with the surrounding lattice. The injection mechanism is facilitated by a unique combination of layout and application biases that result in electric field vectors pulling low-energy minority hole carriers into oxide traps that overlap the drain potential. The effect of this positive charge trapping along the field oxide is to inhibit the RESURF mechanism, while also weakening the gate oxide where it overlaps the drain that ultimately results in a rupture. To quantify the process, a new accelerated aging technique is described that uses the parasitic n-p-n bipolar parallel of the nMOS channel to significantly increase the number of holes while still maintaining the MOS application voltages needed to enable the mechanism. This provides a cost-effective way to accurately accelerate this reliability mechanism with significantly smaller lead times relative to using higher biases and temperatures. This technique is then used with technical computer-aided design (TCAD) analysis to determine the impact of different manufacturing variables, where process controls are introduced for targeted manufacturing limits that can eliminate this mechanism from occurring.

Exploration of Novel Hafnium Oxide (HfO2) Based Plasma-Assisted Gate All Around Carbon Nanotube FET (GAA-CNTFET) for High Sensing Applications

Abstract: The present research aims to implement a hafnium oxide (HfO2) based plasma-assisted gate all around carbon nanotube field effect transistor (GAA-CNTFET) and use it for a better understanding of plasma parameters and their effect on the device. With a more streamlined focus on plasma synthesized (plasma-enhanced chemical vapor deposition technique) CNT for channel material, the intention is to understand how the incorporation of high-k dielectrics leads to enhanced device performance. HfO2 is used as a high-k dielectric to overcome the limitations of conventional silicon dioxide (SiO2) gate dielectric. A comparative analysis has been performed, based on which it can be concluded that using HfO2 leads to improvement in all observed performance metrics; higher drain current, transconductance, output conductance, early voltage, and gate capacitance. Furthermore, by implementing a cavity in the oxide layer and utilizing the concept of dielectric modulation, it can be observed that tailoring the dielectric permittivity of the cavity affects and alters the device's performance characteristics. Better performance and high sensitivity are tilted towards a higher dielectric constant value. This analysis's results help quantify the practical usage of the device for sensing applications in biology, environment and other prominent industries.

Enhancement of carrier mobility in metal-oxide semiconductor field-effect transistors using negative thermal expansion gate electrodes

Abstract: Strained-Si technology is crucial to improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs). To introduce large strain into the channel, we proposed a structure for the negative thermal expansion gate electrode. In this study, we used manganese nitride as the gate material, which is a negative thermal expansion material. The fabricated MOSFETs with the manganese nitride gate showed a 10% increase in electron mobility compared to the MOSFET with the Al gate. The results show that the negative thermal expansion gate technology is promising as a technology booster for MOSFET scaling.

Analytical Investigation of Gate-to-Drain Leakage Current for Junctionless Accumulation-Mode MOSFET

Abstract: Variation of gate-to-drain leakage current as a function of drain-to-source bias is analytically computed for junctionless accumulation mode (JAM) MOSFET considering conduction band electron tunneling. Nanometric dimension of gate dielectric layer is considered with trapezoidal potential profile, and effect of structural dimensions as well as applied bias are considered for the study. Effect of flatband is considered for computation of oxide field along with image charge effect at the oxide-semiconductor interface, which effectively reduces dielectric potential. Simulation reveals leakage in sub-nanometer range can be controlled with lower channel length and width, and of higher oxide thickness, thereby plays key role in improving ON-to-OFF current ratio. Role of applied vertical field is crucial in the evaluation process, where a threshold value exhibit improved performance, contrary to the other simulated findings.